1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
|
From 9503ee4547873f208b70248713bc448a49df54f5 Mon Sep 17 00:00:00 2001
From: Colin Ian King <colin.king@canonical.com>
Date: Wed, 21 Mar 2018 18:26:53 +0000
Subject: [PATCH 3912/4131] drm/amd/pp: use mlck_table.count for array loop
index limit
v2: use temporaries to trivially reduces object size.
The for-loops process data in the mclk_table but use slck_table.count
as the loop index limit. I believe these are cut-n-paste errors from
the previous almost identical loops as indicated by static analysis.
Fix these.
Detected by CoverityScan, CID#1466001 ("Copy-paste error")
Fixes: 5d97cf39ff24 ("drm/amd/pp: Add and initialize OD_dpm_table for CI/VI.")
Fixes: 5e4d4fbea557 ("drm/amd/pp: Implement edit_dpm_table on smu7")
Change-Id: If10eb672ba9e62d9a357866a4c9a3167d8bd2ed6
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 905fc5d..64ed4ab 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -833,6 +833,7 @@ static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
+ struct phm_odn_performance_level *entries;
if (table_info == NULL)
return -EINVAL;
@@ -842,11 +843,11 @@ static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
odn_table->odn_core_clock_dpm_levels.num_of_pl =
data->golden_dpm_table.sclk_table.count;
+ entries = odn_table->odn_core_clock_dpm_levels.entries;
for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
- odn_table->odn_core_clock_dpm_levels.entries[i].clock =
- data->golden_dpm_table.sclk_table.dpm_levels[i].value;
- odn_table->odn_core_clock_dpm_levels.entries[i].enabled = true;
- odn_table->odn_core_clock_dpm_levels.entries[i].vddc = dep_sclk_table->entries[i].vddc;
+ entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value;
+ entries[i].enabled = true;
+ entries[i].vddc = dep_sclk_table->entries[i].vddc;
}
smu7_get_voltage_dependency_table(dep_sclk_table,
@@ -854,11 +855,11 @@ static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
odn_table->odn_memory_clock_dpm_levels.num_of_pl =
data->golden_dpm_table.mclk_table.count;
- for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
- odn_table->odn_memory_clock_dpm_levels.entries[i].clock =
- data->golden_dpm_table.mclk_table.dpm_levels[i].value;
- odn_table->odn_memory_clock_dpm_levels.entries[i].enabled = true;
- odn_table->odn_memory_clock_dpm_levels.entries[i].vddc = dep_mclk_table->entries[i].vddc;
+ entries = odn_table->odn_memory_clock_dpm_levels.entries;
+ for (i=0; i<data->golden_dpm_table.mclk_table.count; i++) {
+ entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value;
+ entries[i].enabled = true;
+ entries[i].vddc = dep_mclk_table->entries[i].vddc;
}
smu7_get_voltage_dependency_table(dep_mclk_table,
@@ -4725,7 +4726,7 @@ static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
}
}
- for (i=0; i<data->dpm_table.sclk_table.count; i++) {
+ for (i=0; i<data->dpm_table.mclk_table.count; i++) {
if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
data->dpm_table.mclk_table.dpm_levels[i].value) {
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
--
2.7.4
|
