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From 75b0c48795e8395dd24c00a346c2dd90a3bd3078 Mon Sep 17 00:00:00 2001
From: Rex Zhu <Rex.Zhu@amd.com>
Date: Fri, 2 Mar 2018 10:52:25 +0800
Subject: [PATCH 3673/4131] drm/amd/pp: Export new smu message for PCC feature
on Vega10
used to set PccThrottleLevel and PccResidencyThreshold
Change-Id: I2a5871de2ad18984022b790bde3a86404b9afd8c
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/smu9.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu9.h b/drivers/gpu/drm/amd/powerplay/inc/smu9.h
index 550ed67..70ac4d4 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu9.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu9.h
@@ -58,7 +58,7 @@
#define FEATURE_FAST_PPT_BIT 26
#define FEATURE_GFX_EDC_BIT 27
#define FEATURE_ACG_BIT 28
-#define FEATURE_SPARE_29_BIT 29
+#define FEATURE_PCC_LIMIT_CONTROL_BIT 29
#define FEATURE_SPARE_30_BIT 30
#define FEATURE_SPARE_31_BIT 31
@@ -94,7 +94,7 @@
#define FEATURE_FAST_PPT_MASK (1 << FAST_PPT_BIT )
#define FEATURE_GFX_EDC_MASK (1 << FEATURE_GFX_EDC_BIT )
#define FEATURE_ACG_MASK (1 << FEATURE_ACG_BIT )
-#define FFEATURE_SPARE_29_MASK (1 << FEATURE_SPARE_29_BIT )
+#define FEATURE_PCC_LIMIT_CONTROL_MASK (1 << FEATURE_PCC_LIMIT_CONTROL_BIT )
#define FFEATURE_SPARE_30_MASK (1 << FEATURE_SPARE_30_BIT )
#define FFEATURE_SPARE_31_MASK (1 << FEATURE_SPARE_31_BIT )
/* Workload types */
--
2.7.4
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