blob: 0049f383978bd1423ff0d3aeedb8675d04ebfe65 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
|
From c43721593a3b6bbcdf85763c3fbe62e709981536 Mon Sep 17 00:00:00 2001
From: Ken Chalmers <ken.chalmers@amd.com>
Date: Thu, 14 Dec 2017 12:43:41 -0500
Subject: [PATCH 3092/4131] drm/amd/display: Fix Maximus pixel clock
programming
Maximus testing now defaults to a 700 MHz emulated dispclk
Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 31280d2..5036b67 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -908,19 +908,9 @@ static bool dce110_program_pix_clk(
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
- unsigned dp_dto_ref_kHz = 600000;
- /* DPREF clock from FPGA TODO: Does FPGA have this value? */
+ unsigned dp_dto_ref_kHz = 700000;
unsigned clock_kHz = pll_settings->actual_pix_clk;
- /* For faster simulation, if mode pixe clock less than 290MHz,
- * pixel clock can be hard coded to 290Mhz. For 4K mode, pixel clock
- * is greater than 500Mhz, need real pixel clock
- * clock_kHz = 290000;
- */
- /* TODO: un-hardcode when we can set display clock properly*/
- /*clock_kHz = pix_clk_params->requested_pix_clk;*/
- clock_kHz = 290000;
-
/* Set DTO values: phase = target clock, modulo = reference clock */
REG_WRITE(PHASE[inst], clock_kHz);
REG_WRITE(MODULO[inst], dp_dto_ref_kHz);
--
2.7.4
|
