1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
|
From 1b5e44ee95307c1db6c43b57508783576305c57e Mon Sep 17 00:00:00 2001
From: Harry Wentland <harry.wentland@amd.com>
Date: Tue, 31 Oct 2017 15:16:56 -0400
Subject: [PATCH 2735/4131] drm/amd/display: Bunch more color indentation
cleanups
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 104 ++++++++++-----------
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 54 ++++-------
2 files changed, 69 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index 543b490..97414ab 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -1183,81 +1183,75 @@ static void program_pwl(
{
uint32_t value;
int retval;
+ uint8_t max_tries = 10;
+ uint8_t counter = 0;
+ uint32_t i = 0;
+ const struct pwl_result_data *rgb = params->rgb_resulted;
- {
- uint8_t max_tries = 10;
- uint8_t counter = 0;
+ /* Power on LUT memory */
+ if (REG(DCFE_MEM_PWR_CTRL))
+ REG_UPDATE(DCFE_MEM_PWR_CTRL,
+ DCP_REGAMMA_MEM_PWR_DIS, 1);
+ else
+ REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
+ REGAMMA_LUT_LIGHT_SLEEP_DIS, 1);
- /* Power on LUT memory */
- if (REG(DCFE_MEM_PWR_CTRL))
- REG_UPDATE(DCFE_MEM_PWR_CTRL,
- DCP_REGAMMA_MEM_PWR_DIS, 1);
- else
- REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
- REGAMMA_LUT_LIGHT_SLEEP_DIS, 1);
-
- while (counter < max_tries) {
- if (REG(DCFE_MEM_PWR_STATUS)) {
- value = REG_READ(DCFE_MEM_PWR_STATUS);
- REG_GET(DCFE_MEM_PWR_STATUS,
- DCP_REGAMMA_MEM_PWR_STATE,
- &retval);
-
- if (retval == 0)
- break;
- ++counter;
- } else {
- value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL);
- REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL,
- REGAMMA_LUT_MEM_PWR_STATE,
- &retval);
-
- if (retval == 0)
- break;
- ++counter;
- }
+ while (counter < max_tries) {
+ if (REG(DCFE_MEM_PWR_STATUS)) {
+ value = REG_READ(DCFE_MEM_PWR_STATUS);
+ REG_GET(DCFE_MEM_PWR_STATUS,
+ DCP_REGAMMA_MEM_PWR_STATE,
+ &retval);
+
+ if (retval == 0)
+ break;
+ ++counter;
+ } else {
+ value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL);
+ REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL,
+ REGAMMA_LUT_MEM_PWR_STATE,
+ &retval);
+
+ if (retval == 0)
+ break;
+ ++counter;
}
+ }
- if (counter == max_tries) {
- dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING,
+ if (counter == max_tries) {
+ dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING,
"%s: regamma lut was not powered on "
"in a timely manner,"
" programming still proceeds\n",
__func__);
- }
}
REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK,
- REGAMMA_LUT_WRITE_EN_MASK, 7);
+ REGAMMA_LUT_WRITE_EN_MASK, 7);
REG_WRITE(REGAMMA_LUT_INDEX, 0);
/* Program REGAMMA_LUT_DATA */
- {
- uint32_t i = 0;
- const struct pwl_result_data *rgb = params->rgb_resulted;
+ while (i != params->hw_points_num) {
- while (i != params->hw_points_num) {
+ REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg);
+ REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg);
+ REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg);
+ REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg);
+ REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg);
+ REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg);
- REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg);
- REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg);
- REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg);
- REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg);
- REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg);
- REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg);
-
- ++rgb;
- ++i;
- }
+ ++rgb;
+ ++i;
}
/* we are done with DCP LUT memory; re-enable low power mode */
if (REG(DCFE_MEM_PWR_CTRL))
REG_UPDATE(DCFE_MEM_PWR_CTRL,
- DCP_REGAMMA_MEM_PWR_DIS, 0);
+ DCP_REGAMMA_MEM_PWR_DIS, 0);
else
REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
- REGAMMA_LUT_LIGHT_SLEEP_DIS, 0);
+ REGAMMA_LUT_LIGHT_SLEEP_DIS, 0);
}
static void regamma_config_regions_and_segments(struct dce_transform *xfm_dce,
@@ -1358,12 +1352,12 @@ void dce110_opp_power_on_regamma_lut(struct transform *xfm,
if (REG(DCFE_MEM_PWR_CTRL))
REG_UPDATE_2(DCFE_MEM_PWR_CTRL,
- DCP_REGAMMA_MEM_PWR_DIS, power_on,
- DCP_LUT_MEM_PWR_DIS, power_on);
+ DCP_REGAMMA_MEM_PWR_DIS, power_on,
+ DCP_LUT_MEM_PWR_DIS, power_on);
else
REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL,
- REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on,
- DCP_LUT_LIGHT_SLEEP_DIS, power_on);
+ REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on,
+ DCP_LUT_LIGHT_SLEEP_DIS, power_on);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index d411d0a..59259cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -432,8 +432,9 @@ static bool convert_to_custom_float(
return true;
}
-static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
- *output_tf, struct pwl_params *regamma_params)
+static bool
+dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
+ struct pwl_params *regamma_params)
{
struct curve_points *arr_points;
struct pwl_result_data *rgb_resulted;
@@ -448,8 +449,7 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
int32_t segment_start, segment_end;
uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points;
- if (output_tf == NULL || regamma_params == NULL ||
- output_tf->type == TF_TYPE_BYPASS)
+ if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
return false;
arr_points = regamma_params->arr_points;
@@ -528,17 +528,14 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
/* last point */
start_index = (segment_end + 25) * 32;
- rgb_resulted[hw_points - 1].red =
- output_tf->tf_pts.red[start_index];
- rgb_resulted[hw_points - 1].green =
- output_tf->tf_pts.green[start_index];
- rgb_resulted[hw_points - 1].blue =
- output_tf->tf_pts.blue[start_index];
+ rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
+ rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
+ rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
- dal_fixed31_32_from_int(segment_start));
+ dal_fixed31_32_from_int(segment_start));
arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
- dal_fixed31_32_from_int(segment_end));
+ dal_fixed31_32_from_int(segment_end));
y_r = rgb_resulted[0].red;
y_g = rgb_resulted[0].green;
@@ -547,9 +544,8 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
arr_points[0].y = y1_min;
- arr_points[0].slope = dal_fixed31_32_div(
- arr_points[0].y,
- arr_points[0].x);
+ arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y,
+ arr_points[0].x);
y_r = rgb_resulted[hw_points - 1].red;
y_g = rgb_resulted[hw_points - 1].green;
@@ -568,12 +564,11 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
/* for PQ, we want to have a straight line from last HW X point,
* and the slope to be such that we hit 1.0 at 10000 nits.
*/
- const struct fixed31_32 end_value =
- dal_fixed31_32_from_int(125);
+ const struct fixed31_32 end_value = dal_fixed31_32_from_int(125);
arr_points[1].slope = dal_fixed31_32_div(
- dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
- dal_fixed31_32_sub(end_value, arr_points[1].x));
+ dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
+ dal_fixed31_32_sub(end_value, arr_points[1].x));
}
regamma_params->hw_points_num = hw_points;
@@ -581,18 +576,15 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
i = 1;
for (k = 0; k < 16 && i < 16; k++) {
if (seg_distr[k] != -1) {
- regamma_params->arr_curve_points[k].segments_num =
- seg_distr[k];
+ regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
regamma_params->arr_curve_points[i].offset =
- regamma_params->arr_curve_points[k].
- offset + (1 << seg_distr[k]);
+ regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
}
i++;
}
if (seg_distr[k] != -1)
- regamma_params->arr_curve_points[k].segments_num =
- seg_distr[k];
+ regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
rgb = rgb_resulted;
rgb_plus_1 = rgb_resulted + 1;
@@ -607,15 +599,9 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
rgb_plus_1->blue = rgb->blue;
- rgb->delta_red = dal_fixed31_32_sub(
- rgb_plus_1->red,
- rgb->red);
- rgb->delta_green = dal_fixed31_32_sub(
- rgb_plus_1->green,
- rgb->green);
- rgb->delta_blue = dal_fixed31_32_sub(
- rgb_plus_1->blue,
- rgb->blue);
+ rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red);
+ rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green);
+ rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue);
++rgb_plus_1;
++rgb;
--
2.7.4
|
