path: root/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2250-drm-amd-include-cleanup-vega10-thm-header-files.patch

From c7df2b1471195533a9c8dec2c48cd4defbaba7e5 Mon Sep 17 00:00:00 2001
From: Feifei Xu <Feifei.Xu@amd.com>
Date: Wed, 22 Nov 2017 14:57:05 +0800
Subject: [PATCH 2250/4131] drm/amd/include:cleanup vega10 thm header files.

Cleanup asic_reg/vega10/THM folder.

Change-Id: Ic4dcd42d5aaf9da38b936467bd340cd67b0235c6
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
---
 .../drm/amd/include/asic_reg/thm/thm_9_0_default.h |  194 +++
 .../drm/amd/include/asic_reg/thm/thm_9_0_offset.h  |  363 ++++++
 .../drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h | 1314 ++++++++++++++++++++
 .../include/asic_reg/vega10/THM/thm_9_0_default.h  |  194 ---
 .../include/asic_reg/vega10/THM/thm_9_0_offset.h   |  363 ------
 .../include/asic_reg/vega10/THM/thm_9_0_sh_mask.h  | 1314 --------------------
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h   |    6 +-
 7 files changed, 1874 insertions(+), 1874 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_default.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_offset.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h
 delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h
 delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h
 delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_default.h
new file mode 100644
index 0000000..0cbae8b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_default.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright (C) 2017  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _thm_9_0_DEFAULT_HEADER
+#define _thm_9_0_DEFAULT_HEADER
+
+
+// addressBlock: thm_thm_SmuThmDec
+#define mmTHM_TCON_CUR_TMP_DEFAULT                                               0x00000000
+#define mmTHM_TCON_HTC_DEFAULT                                                   0x00004000
+#define mmTHM_TCON_THERM_TRIP_DEFAULT                                            0x00000001
+#define mmTHM_GPIO_PROCHOT_CTRL_DEFAULT                                          0x000000f9
+#define mmTHM_GPIO_THERMTRIP_CTRL_DEFAULT                                        0x001000f9
+#define mmTHM_GPIO_PWM_CTRL_DEFAULT                                              0x000000f9
+#define mmTHM_GPIO_TACHIN_CTRL_DEFAULT                                           0x000000f9
+#define mmTHM_GPIO_PUMPOUT_CTRL_DEFAULT                                          0x000000f9
+#define mmTHM_GPIO_PUMPIN_CTRL_DEFAULT                                           0x000000f9
+#define mmTHM_THERMAL_INT_ENA_DEFAULT                                            0x00000000
+#define mmTHM_THERMAL_INT_CTRL_DEFAULT                                           0x0fff0078
+#define mmTHM_THERMAL_INT_STATUS_DEFAULT                                         0x00000000
+#define mmTHM_TMON0_RDIL0_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIL1_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIL2_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIL3_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIL4_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIL5_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIL6_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIL7_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIL8_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIL9_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIL10_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON0_RDIL11_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON0_RDIL12_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON0_RDIL13_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON0_RDIL14_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON0_RDIL15_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON0_RDIR0_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIR1_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIR2_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIR3_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIR4_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIR5_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIR6_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIR7_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIR8_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIR9_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON0_RDIR10_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON0_RDIR11_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON0_RDIR12_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON0_RDIR13_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON0_RDIR14_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON0_RDIR15_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON0_INT_DATA_DEFAULT                                             0x00000000
+#define mmTHM_TMON0_DEBUG_DEFAULT                                                0x00000000
+#define mmTHM_TMON1_RDIL0_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIL1_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIL2_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIL3_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIL4_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIL5_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIL6_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIL7_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIL8_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIL9_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIL10_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON1_RDIL11_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON1_RDIL12_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON1_RDIL13_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON1_RDIL14_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON1_RDIL15_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON1_RDIR0_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIR1_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIR2_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIR3_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIR4_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIR5_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIR6_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIR7_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIR8_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIR9_DATA_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_RDIR10_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON1_RDIR11_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON1_RDIR12_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON1_RDIR13_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON1_RDIR14_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON1_RDIR15_DATA_DEFAULT                                          0x00000000
+#define mmTHM_TMON1_INT_DATA_DEFAULT                                             0x00000000
+#define mmTHM_TMON1_DEBUG_DEFAULT                                                0x00000000
+#define mmTHM_DIE1_TEMP_DEFAULT                                                  0x00000000
+#define mmTHM_DIE2_TEMP_DEFAULT                                                  0x00000000
+#define mmTHM_DIE3_TEMP_DEFAULT                                                  0x00000000
+#define mmCG_MULT_THERMAL_CTRL_DEFAULT                                           0x08400001
+#define mmCG_MULT_THERMAL_STATUS_DEFAULT                                         0x00000000
+#define mmTHM_TMON0_COEFF_DEFAULT                                                0x00024068
+#define mmTHM_TMON1_COEFF_DEFAULT                                                0x00024068
+#define mmCG_FDO_CTRL0_DEFAULT                                                   0x0000642c
+#define mmCG_FDO_CTRL1_DEFAULT                                                   0x001e1f7d
+#define mmCG_FDO_CTRL2_DEFAULT                                                   0x02bf0228
+#define mmCG_TACH_CTRL_DEFAULT                                                   0x00008002
+#define mmCG_TACH_STATUS_DEFAULT                                                 0x00000000
+#define mmCG_THERMAL_STATUS_DEFAULT                                              0x00000000
+#define mmCG_PUMP_CTRL0_DEFAULT                                                  0x0000642c
+#define mmCG_PUMP_CTRL1_DEFAULT                                                  0x001e1f7d
+#define mmCG_PUMP_CTRL2_DEFAULT                                                  0x02bf0228
+#define mmCG_PUMP_TACH_CTRL_DEFAULT                                              0x00008002
+#define mmCG_PUMP_TACH_STATUS_DEFAULT                                            0x00000000
+#define mmCG_PUMP_STATUS_DEFAULT                                                 0x00000000
+#define mmTHM_TCON_LOCAL0_DEFAULT                                                0x00000000
+#define mmTHM_TCON_LOCAL1_DEFAULT                                                0x00000000
+#define mmTHM_TCON_LOCAL2_DEFAULT                                                0x00000060
+#define mmTHM_TCON_LOCAL3_DEFAULT                                                0x00000000
+#define mmTHM_TCON_LOCAL4_DEFAULT                                                0x00000000
+#define mmTHM_TCON_LOCAL5_DEFAULT                                                0x00000000
+#define mmTHM_TCON_LOCAL6_DEFAULT                                                0x00000000
+#define mmTHM_TCON_LOCAL7_DEFAULT                                                0x00000000
+#define mmTHM_TCON_LOCAL8_DEFAULT                                                0x00000000
+#define mmTHM_TCON_LOCAL9_DEFAULT                                                0x00000000
+#define mmTHM_TCON_LOCAL10_DEFAULT                                               0x00000000
+#define mmTHM_TCON_LOCAL11_DEFAULT                                               0x00000000
+#define mmTHM_TCON_LOCAL12_DEFAULT                                               0x00000000
+#define mmTHM_TCON_LOCAL13_DEFAULT                                               0x00000000
+#define mmTHM_BACO_CNTL_DEFAULT                                                  0x00000004
+#define mmTHM_BACO_TIMING0_DEFAULT                                               0x80a06050
+#define mmTHM_BACO_TIMING1_DEFAULT                                               0x1020f070
+#define mmXTAL_CNTL_DEFAULT                                                      0x00006010
+#define mmSBTSI_REMOTE_TEMP_DEFAULT                                              0x00000000
+#define mmSBRMI_CONTROL_DEFAULT                                                  0x00000000
+#define mmSBRMI_COMMAND_DEFAULT                                                  0x00000000
+#define mmSBRMI_WRITE_DATA0_DEFAULT                                              0x00000000
+#define mmSBRMI_WRITE_DATA1_DEFAULT                                              0x00000000
+#define mmSBRMI_WRITE_DATA2_DEFAULT                                              0x00000000
+#define mmSBRMI_READ_DATA0_DEFAULT                                               0x00000000
+#define mmSBRMI_READ_DATA1_DEFAULT                                               0x00000000
+#define mmSBRMI_CORE_EN_NUMBER_DEFAULT                                           0x00000010
+#define mmSBRMI_CORE_EN_STATUS0_DEFAULT                                          0x00000000
+#define mmSBRMI_CORE_EN_STATUS1_DEFAULT                                          0x00000000
+#define mmSBRMI_APIC_STATUS0_DEFAULT                                             0x00000000
+#define mmSBRMI_APIC_STATUS1_DEFAULT                                             0x00000000
+#define mmSBRMI_MCE_STATUS0_DEFAULT                                              0x00000000
+#define mmSBRMI_MCE_STATUS1_DEFAULT                                              0x00000000
+#define mmSMBUS_CNTL0_DEFAULT                                                    0x00030082
+#define mmSMBUS_CNTL1_DEFAULT                                                    0x0000063f
+#define mmSMBUS_BLKWR_CMD_CTRL0_DEFAULT                                          0x12110201
+#define mmSMBUS_BLKWR_CMD_CTRL1_DEFAULT                                          0x0003005a
+#define mmSMBUS_BLKRD_CMD_CTRL0_DEFAULT                                          0x00001303
+#define mmSMBUS_BLKRD_CMD_CTRL1_DEFAULT                                          0x00000000
+#define mmSMBUS_TIMING_CNTL0_DEFAULT                                             0x028a4f5c
+#define mmSMBUS_TIMING_CNTL1_DEFAULT                                             0x08036927
+#define mmSMBUS_TIMING_CNTL2_DEFAULT                                             0x0021e548
+#define mmSMBUS_TRIGGER_CNTL_DEFAULT                                             0x00000000
+#define mmSMBUS_UDID_CNTL0_DEFAULT                                               0x7fffffff
+#define mmSMBUS_UDID_CNTL1_DEFAULT                                               0x00000000
+#define mmSMBUS_UDID_CNTL2_DEFAULT                                               0x00000043
+#define mmSMBUS_BACO_DUMMY_DEFAULT                                               0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE0_LOW_DEFAULT                                     0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE0_HIGH_DEFAULT                                    0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE1_LOW_DEFAULT                                     0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE1_HIGH_DEFAULT                                    0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE2_LOW_DEFAULT                                     0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE2_HIGH_DEFAULT                                    0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE3_LOW_DEFAULT                                     0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE3_HIGH_DEFAULT                                    0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE4_LOW_DEFAULT                                     0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE4_HIGH_DEFAULT                                    0x00000000
+#define mmTHM_GPIO_MACO_EN_CTRL_DEFAULT                                          0x000000f9
+#define mmTHM_BACO_TIMING2_DEFAULT                                               0x00903040
+#define mmTHM_BACO_TIMING_DEFAULT                                                0x00000a8c
+#define mmTHM_TMON0_REMOTE_START_DEFAULT                                         0x00000000
+#define mmTHM_TMON0_REMOTE_END_DEFAULT                                           0x00000000
+#define mmTHM_TMON1_REMOTE_START_DEFAULT                                         0x00000000
+#define mmTHM_TMON1_REMOTE_END_DEFAULT                                           0x00000000
+#define mmTHM_TMON2_REMOTE_START_DEFAULT                                         0x00000000
+#define mmTHM_TMON2_REMOTE_END_DEFAULT                                           0x00000000
+#define mmTHM_TMON3_REMOTE_START_DEFAULT                                         0x00000000
+#define mmTHM_TMON3_REMOTE_END_DEFAULT                                           0x00000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_offset.h
new file mode 100644
index 0000000..3053fd3
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_offset.h
@@ -0,0 +1,363 @@
+/*
+ * Copyright (C) 2017  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _thm_9_0_OFFSET_HEADER
+#define _thm_9_0_OFFSET_HEADER
+
+
+
+// addressBlock: thm_thm_SmuThmDec
+// base address: 0x59800
+#define mmTHM_TCON_CUR_TMP                                                                             0x0000
+#define mmTHM_TCON_CUR_TMP_BASE_IDX                                                                    0
+#define mmTHM_TCON_HTC                                                                                 0x0001
+#define mmTHM_TCON_HTC_BASE_IDX                                                                        0
+#define mmTHM_TCON_THERM_TRIP                                                                          0x0002
+#define mmTHM_TCON_THERM_TRIP_BASE_IDX                                                                 0
+#define mmTHM_GPIO_PROCHOT_CTRL                                                                        0x0004
+#define mmTHM_GPIO_PROCHOT_CTRL_BASE_IDX                                                               0
+#define mmTHM_GPIO_THERMTRIP_CTRL                                                                      0x0005
+#define mmTHM_GPIO_THERMTRIP_CTRL_BASE_IDX                                                             0
+#define mmTHM_GPIO_PWM_CTRL                                                                            0x0006
+#define mmTHM_GPIO_PWM_CTRL_BASE_IDX                                                                   0
+#define mmTHM_GPIO_TACHIN_CTRL                                                                         0x0007
+#define mmTHM_GPIO_TACHIN_CTRL_BASE_IDX                                                                0
+#define mmTHM_GPIO_PUMPOUT_CTRL                                                                        0x0008
+#define mmTHM_GPIO_PUMPOUT_CTRL_BASE_IDX                                                               0
+#define mmTHM_GPIO_PUMPIN_CTRL                                                                         0x0009
+#define mmTHM_GPIO_PUMPIN_CTRL_BASE_IDX                                                                0
+#define mmTHM_THERMAL_INT_ENA                                                                          0x000a
+#define mmTHM_THERMAL_INT_ENA_BASE_IDX                                                                 0
+#define mmTHM_THERMAL_INT_CTRL                                                                         0x000b
+#define mmTHM_THERMAL_INT_CTRL_BASE_IDX                                                                0
+#define mmTHM_THERMAL_INT_STATUS                                                                       0x000c
+#define mmTHM_THERMAL_INT_STATUS_BASE_IDX                                                              0
+#define mmTHM_TMON0_RDIL0_DATA                                                                         0x000d
+#define mmTHM_TMON0_RDIL0_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIL1_DATA                                                                         0x000e
+#define mmTHM_TMON0_RDIL1_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIL2_DATA                                                                         0x000f
+#define mmTHM_TMON0_RDIL2_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIL3_DATA                                                                         0x0010
+#define mmTHM_TMON0_RDIL3_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIL4_DATA                                                                         0x0011
+#define mmTHM_TMON0_RDIL4_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIL5_DATA                                                                         0x0012
+#define mmTHM_TMON0_RDIL5_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIL6_DATA                                                                         0x0013
+#define mmTHM_TMON0_RDIL6_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIL7_DATA                                                                         0x0014
+#define mmTHM_TMON0_RDIL7_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIL8_DATA                                                                         0x0015
+#define mmTHM_TMON0_RDIL8_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIL9_DATA                                                                         0x0016
+#define mmTHM_TMON0_RDIL9_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIL10_DATA                                                                        0x0017
+#define mmTHM_TMON0_RDIL10_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON0_RDIL11_DATA                                                                        0x0018
+#define mmTHM_TMON0_RDIL11_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON0_RDIL12_DATA                                                                        0x0019
+#define mmTHM_TMON0_RDIL12_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON0_RDIL13_DATA                                                                        0x001a
+#define mmTHM_TMON0_RDIL13_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON0_RDIL14_DATA                                                                        0x001b
+#define mmTHM_TMON0_RDIL14_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON0_RDIL15_DATA                                                                        0x001c
+#define mmTHM_TMON0_RDIL15_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON0_RDIR0_DATA                                                                         0x001d
+#define mmTHM_TMON0_RDIR0_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIR1_DATA                                                                         0x001e
+#define mmTHM_TMON0_RDIR1_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIR2_DATA                                                                         0x001f
+#define mmTHM_TMON0_RDIR2_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIR3_DATA                                                                         0x0020
+#define mmTHM_TMON0_RDIR3_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIR4_DATA                                                                         0x0021
+#define mmTHM_TMON0_RDIR4_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIR5_DATA                                                                         0x0022
+#define mmTHM_TMON0_RDIR5_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIR6_DATA                                                                         0x0023
+#define mmTHM_TMON0_RDIR6_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIR7_DATA                                                                         0x0024
+#define mmTHM_TMON0_RDIR7_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIR8_DATA                                                                         0x0025
+#define mmTHM_TMON0_RDIR8_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIR9_DATA                                                                         0x0026
+#define mmTHM_TMON0_RDIR9_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON0_RDIR10_DATA                                                                        0x0027
+#define mmTHM_TMON0_RDIR10_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON0_RDIR11_DATA                                                                        0x0028
+#define mmTHM_TMON0_RDIR11_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON0_RDIR12_DATA                                                                        0x0029
+#define mmTHM_TMON0_RDIR12_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON0_RDIR13_DATA                                                                        0x002a
+#define mmTHM_TMON0_RDIR13_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON0_RDIR14_DATA                                                                        0x002b
+#define mmTHM_TMON0_RDIR14_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON0_RDIR15_DATA                                                                        0x002c
+#define mmTHM_TMON0_RDIR15_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON0_INT_DATA                                                                           0x002d
+#define mmTHM_TMON0_INT_DATA_BASE_IDX                                                                  0
+#define mmTHM_TMON0_DEBUG                                                                              0x0030
+#define mmTHM_TMON0_DEBUG_BASE_IDX                                                                     0
+#define mmTHM_TMON1_RDIL0_DATA                                                                         0x0031
+#define mmTHM_TMON1_RDIL0_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIL1_DATA                                                                         0x0032
+#define mmTHM_TMON1_RDIL1_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIL2_DATA                                                                         0x0033
+#define mmTHM_TMON1_RDIL2_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIL3_DATA                                                                         0x0034
+#define mmTHM_TMON1_RDIL3_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIL4_DATA                                                                         0x0035
+#define mmTHM_TMON1_RDIL4_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIL5_DATA                                                                         0x0036
+#define mmTHM_TMON1_RDIL5_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIL6_DATA                                                                         0x0037
+#define mmTHM_TMON1_RDIL6_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIL7_DATA                                                                         0x0038
+#define mmTHM_TMON1_RDIL7_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIL8_DATA                                                                         0x0039
+#define mmTHM_TMON1_RDIL8_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIL9_DATA                                                                         0x003a
+#define mmTHM_TMON1_RDIL9_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIL10_DATA                                                                        0x003b
+#define mmTHM_TMON1_RDIL10_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON1_RDIL11_DATA                                                                        0x003c
+#define mmTHM_TMON1_RDIL11_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON1_RDIL12_DATA                                                                        0x003d
+#define mmTHM_TMON1_RDIL12_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON1_RDIL13_DATA                                                                        0x003e
+#define mmTHM_TMON1_RDIL13_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON1_RDIL14_DATA                                                                        0x003f
+#define mmTHM_TMON1_RDIL14_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON1_RDIL15_DATA                                                                        0x0040
+#define mmTHM_TMON1_RDIL15_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON1_RDIR0_DATA                                                                         0x0041
+#define mmTHM_TMON1_RDIR0_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIR1_DATA                                                                         0x0042
+#define mmTHM_TMON1_RDIR1_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIR2_DATA                                                                         0x0043
+#define mmTHM_TMON1_RDIR2_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIR3_DATA                                                                         0x0044
+#define mmTHM_TMON1_RDIR3_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIR4_DATA                                                                         0x0045
+#define mmTHM_TMON1_RDIR4_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIR5_DATA                                                                         0x0046
+#define mmTHM_TMON1_RDIR5_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIR6_DATA                                                                         0x0047
+#define mmTHM_TMON1_RDIR6_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIR7_DATA                                                                         0x0048
+#define mmTHM_TMON1_RDIR7_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIR8_DATA                                                                         0x0049
+#define mmTHM_TMON1_RDIR8_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIR9_DATA                                                                         0x004a
+#define mmTHM_TMON1_RDIR9_DATA_BASE_IDX                                                                0
+#define mmTHM_TMON1_RDIR10_DATA                                                                        0x004b
+#define mmTHM_TMON1_RDIR10_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON1_RDIR11_DATA                                                                        0x004c
+#define mmTHM_TMON1_RDIR11_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON1_RDIR12_DATA                                                                        0x004d
+#define mmTHM_TMON1_RDIR12_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON1_RDIR13_DATA                                                                        0x004e
+#define mmTHM_TMON1_RDIR13_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON1_RDIR14_DATA                                                                        0x004f
+#define mmTHM_TMON1_RDIR14_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON1_RDIR15_DATA                                                                        0x0050
+#define mmTHM_TMON1_RDIR15_DATA_BASE_IDX                                                               0
+#define mmTHM_TMON1_INT_DATA                                                                           0x0051
+#define mmTHM_TMON1_INT_DATA_BASE_IDX                                                                  0
+#define mmTHM_TMON1_DEBUG                                                                              0x0054
+#define mmTHM_TMON1_DEBUG_BASE_IDX                                                                     0
+#define mmTHM_DIE1_TEMP                                                                                0x0055
+#define mmTHM_DIE1_TEMP_BASE_IDX                                                                       0
+#define mmTHM_DIE2_TEMP                                                                                0x0056
+#define mmTHM_DIE2_TEMP_BASE_IDX                                                                       0
+#define mmTHM_DIE3_TEMP                                                                                0x0057
+#define mmTHM_DIE3_TEMP_BASE_IDX                                                                       0
+#define mmCG_MULT_THERMAL_CTRL                                                                         0x0059
+#define mmCG_MULT_THERMAL_CTRL_BASE_IDX                                                                0
+#define mmCG_MULT_THERMAL_STATUS                                                                       0x005a
+#define mmCG_MULT_THERMAL_STATUS_BASE_IDX                                                              0
+#define mmTHM_TMON0_COEFF                                                                              0x005e
+#define mmTHM_TMON0_COEFF_BASE_IDX                                                                     0
+#define mmTHM_TMON1_COEFF                                                                              0x005f
+#define mmTHM_TMON1_COEFF_BASE_IDX                                                                     0
+#define mmCG_FDO_CTRL0                                                                                 0x0062
+#define mmCG_FDO_CTRL0_BASE_IDX                                                                        0
+#define mmCG_FDO_CTRL1                                                                                 0x0063
+#define mmCG_FDO_CTRL1_BASE_IDX                                                                        0
+#define mmCG_FDO_CTRL2                                                                                 0x0064
+#define mmCG_FDO_CTRL2_BASE_IDX                                                                        0
+#define mmCG_TACH_CTRL                                                                                 0x0065
+#define mmCG_TACH_CTRL_BASE_IDX                                                                        0
+#define mmCG_TACH_STATUS                                                                               0x0066
+#define mmCG_TACH_STATUS_BASE_IDX                                                                      0
+#define mmCG_THERMAL_STATUS                                                                            0x0067
+#define mmCG_THERMAL_STATUS_BASE_IDX                                                                   0
+#define mmCG_PUMP_CTRL0                                                                                0x0068
+#define mmCG_PUMP_CTRL0_BASE_IDX                                                                       0
+#define mmCG_PUMP_CTRL1                                                                                0x0069
+#define mmCG_PUMP_CTRL1_BASE_IDX                                                                       0
+#define mmCG_PUMP_CTRL2                                                                                0x006a
+#define mmCG_PUMP_CTRL2_BASE_IDX                                                                       0
+#define mmCG_PUMP_TACH_CTRL                                                                            0x006b
+#define mmCG_PUMP_TACH_CTRL_BASE_IDX                                                                   0
+#define mmCG_PUMP_TACH_STATUS                                                                          0x006c
+#define mmCG_PUMP_TACH_STATUS_BASE_IDX                                                                 0
+#define mmCG_PUMP_STATUS                                                                               0x006d
+#define mmCG_PUMP_STATUS_BASE_IDX                                                                      0
+#define mmTHM_TCON_LOCAL0                                                                              0x006e
+#define mmTHM_TCON_LOCAL0_BASE_IDX                                                                     0
+#define mmTHM_TCON_LOCAL1                                                                              0x006f
+#define mmTHM_TCON_LOCAL1_BASE_IDX                                                                     0
+#define mmTHM_TCON_LOCAL2                                                                              0x0070
+#define mmTHM_TCON_LOCAL2_BASE_IDX                                                                     0
+#define mmTHM_TCON_LOCAL3                                                                              0x0071
+#define mmTHM_TCON_LOCAL3_BASE_IDX                                                                     0
+#define mmTHM_TCON_LOCAL4                                                                              0x0072
+#define mmTHM_TCON_LOCAL4_BASE_IDX                                                                     0
+#define mmTHM_TCON_LOCAL5                                                                              0x0073
+#define mmTHM_TCON_LOCAL5_BASE_IDX                                                                     0
+#define mmTHM_TCON_LOCAL6                                                                              0x0074
+#define mmTHM_TCON_LOCAL6_BASE_IDX                                                                     0
+#define mmTHM_TCON_LOCAL7                                                                              0x0075
+#define mmTHM_TCON_LOCAL7_BASE_IDX                                                                     0
+#define mmTHM_TCON_LOCAL8                                                                              0x0076
+#define mmTHM_TCON_LOCAL8_BASE_IDX                                                                     0
+#define mmTHM_TCON_LOCAL9                                                                              0x0077
+#define mmTHM_TCON_LOCAL9_BASE_IDX                                                                     0
+#define mmTHM_TCON_LOCAL10                                                                             0x0078
+#define mmTHM_TCON_LOCAL10_BASE_IDX                                                                    0
+#define mmTHM_TCON_LOCAL11                                                                             0x0079
+#define mmTHM_TCON_LOCAL11_BASE_IDX                                                                    0
+#define mmTHM_TCON_LOCAL12                                                                             0x007a
+#define mmTHM_TCON_LOCAL12_BASE_IDX                                                                    0
+#define mmTHM_TCON_LOCAL13                                                                             0x007b
+#define mmTHM_TCON_LOCAL13_BASE_IDX                                                                    0
+#define mmTHM_BACO_CNTL                                                                                0x007c
+#define mmTHM_BACO_CNTL_BASE_IDX                                                                       0
+#define mmTHM_BACO_TIMING0                                                                             0x007d
+#define mmTHM_BACO_TIMING0_BASE_IDX                                                                    0
+#define mmTHM_BACO_TIMING1                                                                             0x007e
+#define mmTHM_BACO_TIMING1_BASE_IDX                                                                    0
+#define mmXTAL_CNTL                                                                                    0x007f
+#define mmXTAL_CNTL_BASE_IDX                                                                           0
+#define mmSBTSI_REMOTE_TEMP                                                                            0x008a
+#define mmSBTSI_REMOTE_TEMP_BASE_IDX                                                                   0
+#define mmSBRMI_CONTROL                                                                                0x008b
+#define mmSBRMI_CONTROL_BASE_IDX                                                                       0
+#define mmSBRMI_COMMAND                                                                                0x008c
+#define mmSBRMI_COMMAND_BASE_IDX                                                                       0
+#define mmSBRMI_WRITE_DATA0                                                                            0x008d
+#define mmSBRMI_WRITE_DATA0_BASE_IDX                                                                   0
+#define mmSBRMI_WRITE_DATA1                                                                            0x008e
+#define mmSBRMI_WRITE_DATA1_BASE_IDX                                                                   0
+#define mmSBRMI_WRITE_DATA2                                                                            0x008f
+#define mmSBRMI_WRITE_DATA2_BASE_IDX                                                                   0
+#define mmSBRMI_READ_DATA0                                                                             0x0090
+#define mmSBRMI_READ_DATA0_BASE_IDX                                                                    0
+#define mmSBRMI_READ_DATA1                                                                             0x0091
+#define mmSBRMI_READ_DATA1_BASE_IDX                                                                    0
+#define mmSBRMI_CORE_EN_NUMBER                                                                         0x0092
+#define mmSBRMI_CORE_EN_NUMBER_BASE_IDX                                                                0
+#define mmSBRMI_CORE_EN_STATUS0                                                                        0x0093
+#define mmSBRMI_CORE_EN_STATUS0_BASE_IDX                                                               0
+#define mmSBRMI_CORE_EN_STATUS1                                                                        0x0094
+#define mmSBRMI_CORE_EN_STATUS1_BASE_IDX                                                               0
+#define mmSBRMI_APIC_STATUS0                                                                           0x0095
+#define mmSBRMI_APIC_STATUS0_BASE_IDX                                                                  0
+#define mmSBRMI_APIC_STATUS1                                                                           0x0096
+#define mmSBRMI_APIC_STATUS1_BASE_IDX                                                                  0
+#define mmSBRMI_MCE_STATUS0                                                                            0x0097
+#define mmSBRMI_MCE_STATUS0_BASE_IDX                                                                   0
+#define mmSBRMI_MCE_STATUS1                                                                            0x0098
+#define mmSBRMI_MCE_STATUS1_BASE_IDX                                                                   0
+#define mmSMBUS_CNTL0                                                                                  0x0099
+#define mmSMBUS_CNTL0_BASE_IDX                                                                         0
+#define mmSMBUS_CNTL1                                                                                  0x009a
+#define mmSMBUS_CNTL1_BASE_IDX                                                                         0
+#define mmSMBUS_BLKWR_CMD_CTRL0                                                                        0x009b
+#define mmSMBUS_BLKWR_CMD_CTRL0_BASE_IDX                                                               0
+#define mmSMBUS_BLKWR_CMD_CTRL1                                                                        0x009c
+#define mmSMBUS_BLKWR_CMD_CTRL1_BASE_IDX                                                               0
+#define mmSMBUS_BLKRD_CMD_CTRL0                                                                        0x009d
+#define mmSMBUS_BLKRD_CMD_CTRL0_BASE_IDX                                                               0
+#define mmSMBUS_BLKRD_CMD_CTRL1                                                                        0x009e
+#define mmSMBUS_BLKRD_CMD_CTRL1_BASE_IDX                                                               0
+#define mmSMBUS_TIMING_CNTL0                                                                           0x009f
+#define mmSMBUS_TIMING_CNTL0_BASE_IDX                                                                  0
+#define mmSMBUS_TIMING_CNTL1                                                                           0x00a0
+#define mmSMBUS_TIMING_CNTL1_BASE_IDX                                                                  0
+#define mmSMBUS_TIMING_CNTL2                                                                           0x00a1
+#define mmSMBUS_TIMING_CNTL2_BASE_IDX                                                                  0
+#define mmSMBUS_TRIGGER_CNTL                                                                           0x00a2
+#define mmSMBUS_TRIGGER_CNTL_BASE_IDX                                                                  0
+#define mmSMBUS_UDID_CNTL0                                                                             0x00a3
+#define mmSMBUS_UDID_CNTL0_BASE_IDX                                                                    0
+#define mmSMBUS_UDID_CNTL1                                                                             0x00a4
+#define mmSMBUS_UDID_CNTL1_BASE_IDX                                                                    0
+#define mmSMBUS_UDID_CNTL2                                                                             0x00a5
+#define mmSMBUS_UDID_CNTL2_BASE_IDX                                                                    0
+#define mmSMBUS_BACO_DUMMY                                                                             0x00a8
+#define mmSMBUS_BACO_DUMMY_BASE_IDX                                                                    0
+#define mmSMBUS_BACO_ADDR_RANGE0_LOW                                                                   0x00a9
+#define mmSMBUS_BACO_ADDR_RANGE0_LOW_BASE_IDX                                                          0
+#define mmSMBUS_BACO_ADDR_RANGE0_HIGH                                                                  0x00aa
+#define mmSMBUS_BACO_ADDR_RANGE0_HIGH_BASE_IDX                                                         0
+#define mmSMBUS_BACO_ADDR_RANGE1_LOW                                                                   0x00ab
+#define mmSMBUS_BACO_ADDR_RANGE1_LOW_BASE_IDX                                                          0
+#define mmSMBUS_BACO_ADDR_RANGE1_HIGH                                                                  0x00ac
+#define mmSMBUS_BACO_ADDR_RANGE1_HIGH_BASE_IDX                                                         0
+#define mmSMBUS_BACO_ADDR_RANGE2_LOW                                                                   0x00ad
+#define mmSMBUS_BACO_ADDR_RANGE2_LOW_BASE_IDX                                                          0
+#define mmSMBUS_BACO_ADDR_RANGE2_HIGH                                                                  0x00ae
+#define mmSMBUS_BACO_ADDR_RANGE2_HIGH_BASE_IDX                                                         0
+#define mmSMBUS_BACO_ADDR_RANGE3_LOW                                                                   0x00af
+#define mmSMBUS_BACO_ADDR_RANGE3_LOW_BASE_IDX                                                          0
+#define mmSMBUS_BACO_ADDR_RANGE3_HIGH                                                                  0x00b0
+#define mmSMBUS_BACO_ADDR_RANGE3_HIGH_BASE_IDX                                                         0
+#define mmSMBUS_BACO_ADDR_RANGE4_LOW                                                                   0x00b1
+#define mmSMBUS_BACO_ADDR_RANGE4_LOW_BASE_IDX                                                          0
+#define mmSMBUS_BACO_ADDR_RANGE4_HIGH                                                                  0x00b2
+#define mmSMBUS_BACO_ADDR_RANGE4_HIGH_BASE_IDX                                                         0
+#define mmTHM_GPIO_MACO_EN_CTRL                                                                        0x00bd
+#define mmTHM_GPIO_MACO_EN_CTRL_BASE_IDX                                                               0
+#define mmTHM_BACO_TIMING2                                                                             0x00bf
+#define mmTHM_BACO_TIMING2_BASE_IDX                                                                    0
+#define mmTHM_BACO_TIMING                                                                              0x00c0
+#define mmTHM_BACO_TIMING_BASE_IDX                                                                     0
+#define mmTHM_TMON0_REMOTE_START                                                                       0x0100
+#define mmTHM_TMON0_REMOTE_START_BASE_IDX                                                              0
+#define mmTHM_TMON0_REMOTE_END                                                                         0x013f
+#define mmTHM_TMON0_REMOTE_END_BASE_IDX                                                                0
+#define mmTHM_TMON1_REMOTE_START                                                                       0x0140
+#define mmTHM_TMON1_REMOTE_START_BASE_IDX                                                              0
+#define mmTHM_TMON1_REMOTE_END                                                                         0x017f
+#define mmTHM_TMON1_REMOTE_END_BASE_IDX                                                                0
+#define mmTHM_TMON2_REMOTE_START                                                                       0x0180
+#define mmTHM_TMON2_REMOTE_START_BASE_IDX                                                              0
+#define mmTHM_TMON2_REMOTE_END                                                                         0x01bf
+#define mmTHM_TMON2_REMOTE_END_BASE_IDX                                                                0
+#define mmTHM_TMON3_REMOTE_START                                                                       0x01c0
+#define mmTHM_TMON3_REMOTE_START_BASE_IDX                                                              0
+#define mmTHM_TMON3_REMOTE_END                                                                         0x01ff
+#define mmTHM_TMON3_REMOTE_END_BASE_IDX                                                                0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h
new file mode 100644
index 0000000..f0306c5
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h
@@ -0,0 +1,1314 @@
+/*
+ * Copyright (C) 2017  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _thm_9_0_SH_MASK_HEADER
+#define _thm_9_0_SH_MASK_HEADER
+
+
+// addressBlock: thm_thm_SmuThmDec
+//THM_TCON_CUR_TMP
+#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT                                                             0x0
+#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT                                                              0x5
+#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT                                                               0x7
+#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT                                                             0x8
+#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT                                                              0x10
+#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT                                                         0x12
+#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT                                                           0x13
+#define THM_TCON_CUR_TMP__MCM_EN__SHIFT                                                                       0x14
+#define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT                                                                     0x15
+#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK                                                               0x0000001FL
+#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK                                                                0x00000060L
+#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK                                                                 0x00000080L
+#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK                                                               0x00001F00L
+#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK                                                                0x00030000L
+#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK                                                           0x00040000L
+#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK                                                             0x00080000L
+#define THM_TCON_CUR_TMP__MCM_EN_MASK                                                                         0x00100000L
+#define THM_TCON_CUR_TMP__CUR_TEMP_MASK                                                                       0xFFE00000L
+//THM_TCON_HTC
+#define THM_TCON_HTC__HTC_EN__SHIFT                                                                           0x0
+#define THM_TCON_HTC__EXTERNAL_PROCHOT__SHIFT                                                                 0x2
+#define THM_TCON_HTC__INTERNAL_PROCHOT__SHIFT                                                                 0x3
+#define THM_TCON_HTC__HTC_ACTIVE__SHIFT                                                                       0x4
+#define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT                                                                   0x5
+#define THM_TCON_HTC__HTC_DIAG__SHIFT                                                                         0x8
+#define THM_TCON_HTC__DIS_PROCHOT_PIN__SHIFT                                                                  0x9
+#define THM_TCON_HTC__HTC_TO_IH_EN__SHIFT                                                                     0xa
+#define THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT                                                                 0xb
+#define THM_TCON_HTC__PROCHOT_EVENT_SRC__SHIFT                                                                0xc
+#define THM_TCON_HTC__HTC_TMP_LMT__SHIFT                                                                      0x10
+#define THM_TCON_HTC__HTC_HYST_LMT__SHIFT                                                                     0x17
+#define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT                                                                     0x1b
+#define THM_TCON_HTC__HTC_EN_MASK                                                                             0x00000001L
+#define THM_TCON_HTC__EXTERNAL_PROCHOT_MASK                                                                   0x00000004L
+#define THM_TCON_HTC__INTERNAL_PROCHOT_MASK                                                                   0x00000008L
+#define THM_TCON_HTC__HTC_ACTIVE_MASK                                                                         0x00000010L
+#define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK                                                                     0x00000020L
+#define THM_TCON_HTC__HTC_DIAG_MASK                                                                           0x00000100L
+#define THM_TCON_HTC__DIS_PROCHOT_PIN_MASK                                                                    0x00000200L
+#define THM_TCON_HTC__HTC_TO_IH_EN_MASK                                                                       0x00000400L
+#define THM_TCON_HTC__PROCHOT_TO_IH_EN_MASK                                                                   0x00000800L
+#define THM_TCON_HTC__PROCHOT_EVENT_SRC_MASK                                                                  0x00007000L
+#define THM_TCON_HTC__HTC_TMP_LMT_MASK                                                                        0x007F0000L
+#define THM_TCON_HTC__HTC_HYST_LMT_MASK                                                                       0x07800000L
+#define THM_TCON_HTC__HTC_SLEW_SEL_MASK                                                                       0x18000000L
+//THM_TCON_THERM_TRIP
+#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT                                                          0x0
+#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT                                                                  0x1
+#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT                                                    0x2
+#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT                                                            0x3
+#define THM_TCON_THERM_TRIP__RSVD2__SHIFT                                                                     0x4
+#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT                                                               0x5
+#define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT                                                              0x6
+#define THM_TCON_THERM_TRIP__RSVD3__SHIFT                                                                     0xe
+#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT                                                               0x1f
+#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK                                                            0x00000001L
+#define THM_TCON_THERM_TRIP__THERM_TP_MASK                                                                    0x00000002L
+#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK                                                      0x00000004L
+#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK                                                              0x00000008L
+#define THM_TCON_THERM_TRIP__RSVD2_MASK                                                                       0x00000010L
+#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK                                                                 0x00000020L
+#define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK                                                                0x00003FC0L
+#define THM_TCON_THERM_TRIP__RSVD3_MASK                                                                       0x7FFFC000L
+#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK                                                                 0x80000000L
+//THM_GPIO_PROCHOT_CTRL
+#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL__SHIFT                                                                0x0
+#define THM_GPIO_PROCHOT_CTRL__PD__SHIFT                                                                      0x1
+#define THM_GPIO_PROCHOT_CTRL__PU__SHIFT                                                                      0x2
+#define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT                                                                  0x3
+#define THM_GPIO_PROCHOT_CTRL__S0__SHIFT                                                                      0x4
+#define THM_GPIO_PROCHOT_CTRL__S1__SHIFT                                                                      0x5
+#define THM_GPIO_PROCHOT_CTRL__RXEN__SHIFT                                                                    0x6
+#define THM_GPIO_PROCHOT_CTRL__RXSEL0__SHIFT                                                                  0x7
+#define THM_GPIO_PROCHOT_CTRL__RXSEL1__SHIFT                                                                  0x8
+#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT                                                             0x10
+#define THM_GPIO_PROCHOT_CTRL__OE__SHIFT                                                                      0x11
+#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT                                                              0x12
+#define THM_GPIO_PROCHOT_CTRL__A__SHIFT                                                                       0x13
+#define THM_GPIO_PROCHOT_CTRL__Y__SHIFT                                                                       0x1f
+#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL_MASK                                                                  0x00000001L
+#define THM_GPIO_PROCHOT_CTRL__PD_MASK                                                                        0x00000002L
+#define THM_GPIO_PROCHOT_CTRL__PU_MASK                                                                        0x00000004L
+#define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK                                                                    0x00000008L
+#define THM_GPIO_PROCHOT_CTRL__S0_MASK                                                                        0x00000010L
+#define THM_GPIO_PROCHOT_CTRL__S1_MASK                                                                        0x00000020L
+#define THM_GPIO_PROCHOT_CTRL__RXEN_MASK                                                                      0x00000040L
+#define THM_GPIO_PROCHOT_CTRL__RXSEL0_MASK                                                                    0x00000080L
+#define THM_GPIO_PROCHOT_CTRL__RXSEL1_MASK                                                                    0x00000100L
+#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK                                                               0x00010000L
+#define THM_GPIO_PROCHOT_CTRL__OE_MASK                                                                        0x00020000L
+#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK                                                                0x00040000L
+#define THM_GPIO_PROCHOT_CTRL__A_MASK                                                                         0x00080000L
+#define THM_GPIO_PROCHOT_CTRL__Y_MASK                                                                         0x80000000L
+//THM_GPIO_THERMTRIP_CTRL
+#define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL__SHIFT                                                              0x0
+#define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT                                                                    0x1
+#define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT                                                                    0x2
+#define THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT                                                                0x3
+#define THM_GPIO_THERMTRIP_CTRL__S0__SHIFT                                                                    0x4
+#define THM_GPIO_THERMTRIP_CTRL__S1__SHIFT                                                                    0x5
+#define THM_GPIO_THERMTRIP_CTRL__RXEN__SHIFT                                                                  0x6
+#define THM_GPIO_THERMTRIP_CTRL__RXSEL0__SHIFT                                                                0x7
+#define THM_GPIO_THERMTRIP_CTRL__RXSEL1__SHIFT                                                                0x8
+#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT                                                           0x10
+#define THM_GPIO_THERMTRIP_CTRL__OE__SHIFT                                                                    0x11
+#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT                                                            0x12
+#define THM_GPIO_THERMTRIP_CTRL__A__SHIFT                                                                     0x13
+#define THM_GPIO_THERMTRIP_CTRL__CTFEN__SHIFT                                                                 0x14
+#define THM_GPIO_THERMTRIP_CTRL__Y__SHIFT                                                                     0x1f
+#define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL_MASK                                                                0x00000001L
+#define THM_GPIO_THERMTRIP_CTRL__PD_MASK                                                                      0x00000002L
+#define THM_GPIO_THERMTRIP_CTRL__PU_MASK                                                                      0x00000004L
+#define THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK                                                                  0x00000008L
+#define THM_GPIO_THERMTRIP_CTRL__S0_MASK                                                                      0x00000010L
+#define THM_GPIO_THERMTRIP_CTRL__S1_MASK                                                                      0x00000020L
+#define THM_GPIO_THERMTRIP_CTRL__RXEN_MASK                                                                    0x00000040L
+#define THM_GPIO_THERMTRIP_CTRL__RXSEL0_MASK                                                                  0x00000080L
+#define THM_GPIO_THERMTRIP_CTRL__RXSEL1_MASK                                                                  0x00000100L
+#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK                                                             0x00010000L
+#define THM_GPIO_THERMTRIP_CTRL__OE_MASK                                                                      0x00020000L
+#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK                                                              0x00040000L
+#define THM_GPIO_THERMTRIP_CTRL__A_MASK                                                                       0x00080000L
+#define THM_GPIO_THERMTRIP_CTRL__CTFEN_MASK                                                                   0x00100000L
+#define THM_GPIO_THERMTRIP_CTRL__Y_MASK                                                                       0x80000000L
+//THM_GPIO_PWM_CTRL
+#define THM_GPIO_PWM_CTRL__TXIMPSEL__SHIFT                                                                    0x0
+#define THM_GPIO_PWM_CTRL__PD__SHIFT                                                                          0x1
+#define THM_GPIO_PWM_CTRL__PU__SHIFT                                                                          0x2
+#define THM_GPIO_PWM_CTRL__SCHMEN__SHIFT                                                                      0x3
+#define THM_GPIO_PWM_CTRL__S0__SHIFT                                                                          0x4
+#define THM_GPIO_PWM_CTRL__S1__SHIFT                                                                          0x5
+#define THM_GPIO_PWM_CTRL__RXEN__SHIFT                                                                        0x6
+#define THM_GPIO_PWM_CTRL__RXSEL0__SHIFT                                                                      0x7
+#define THM_GPIO_PWM_CTRL__RXSEL1__SHIFT                                                                      0x8
+#define THM_GPIO_PWM_CTRL__OE_OVERRIDE__SHIFT                                                                 0x10
+#define THM_GPIO_PWM_CTRL__OE__SHIFT                                                                          0x11
+#define THM_GPIO_PWM_CTRL__A_OVERRIDE__SHIFT                                                                  0x12
+#define THM_GPIO_PWM_CTRL__A__SHIFT                                                                           0x13
+#define THM_GPIO_PWM_CTRL__Y__SHIFT                                                                           0x1f
+#define THM_GPIO_PWM_CTRL__TXIMPSEL_MASK                                                                      0x00000001L
+#define THM_GPIO_PWM_CTRL__PD_MASK                                                                            0x00000002L
+#define THM_GPIO_PWM_CTRL__PU_MASK                                                                            0x00000004L
+#define THM_GPIO_PWM_CTRL__SCHMEN_MASK                                                                        0x00000008L
+#define THM_GPIO_PWM_CTRL__S0_MASK                                                                            0x00000010L
+#define THM_GPIO_PWM_CTRL__S1_MASK                                                                            0x00000020L
+#define THM_GPIO_PWM_CTRL__RXEN_MASK                                                                          0x00000040L
+#define THM_GPIO_PWM_CTRL__RXSEL0_MASK                                                                        0x00000080L
+#define THM_GPIO_PWM_CTRL__RXSEL1_MASK                                                                        0x00000100L
+#define THM_GPIO_PWM_CTRL__OE_OVERRIDE_MASK                                                                   0x00010000L
+#define THM_GPIO_PWM_CTRL__OE_MASK                                                                            0x00020000L
+#define THM_GPIO_PWM_CTRL__A_OVERRIDE_MASK                                                                    0x00040000L
+#define THM_GPIO_PWM_CTRL__A_MASK                                                                             0x00080000L
+#define THM_GPIO_PWM_CTRL__Y_MASK                                                                             0x80000000L
+//THM_GPIO_TACHIN_CTRL
+#define THM_GPIO_TACHIN_CTRL__TXIMPSEL__SHIFT                                                                 0x0
+#define THM_GPIO_TACHIN_CTRL__PD__SHIFT                                                                       0x1
+#define THM_GPIO_TACHIN_CTRL__PU__SHIFT                                                                       0x2
+#define THM_GPIO_TACHIN_CTRL__SCHMEN__SHIFT                                                                   0x3
+#define THM_GPIO_TACHIN_CTRL__S0__SHIFT                                                                       0x4
+#define THM_GPIO_TACHIN_CTRL__S1__SHIFT                                                                       0x5
+#define THM_GPIO_TACHIN_CTRL__RXEN__SHIFT                                                                     0x6
+#define THM_GPIO_TACHIN_CTRL__RXSEL0__SHIFT                                                                   0x7
+#define THM_GPIO_TACHIN_CTRL__RXSEL1__SHIFT                                                                   0x8
+#define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE__SHIFT                                                              0x10
+#define THM_GPIO_TACHIN_CTRL__OE__SHIFT                                                                       0x11
+#define THM_GPIO_TACHIN_CTRL__A_OVERRIDE__SHIFT                                                               0x12
+#define THM_GPIO_TACHIN_CTRL__A__SHIFT                                                                        0x13
+#define THM_GPIO_TACHIN_CTRL__Y__SHIFT                                                                        0x1f
+#define THM_GPIO_TACHIN_CTRL__TXIMPSEL_MASK                                                                   0x00000001L
+#define THM_GPIO_TACHIN_CTRL__PD_MASK                                                                         0x00000002L
+#define THM_GPIO_TACHIN_CTRL__PU_MASK                                                                         0x00000004L
+#define THM_GPIO_TACHIN_CTRL__SCHMEN_MASK                                                                     0x00000008L
+#define THM_GPIO_TACHIN_CTRL__S0_MASK                                                                         0x00000010L
+#define THM_GPIO_TACHIN_CTRL__S1_MASK                                                                         0x00000020L
+#define THM_GPIO_TACHIN_CTRL__RXEN_MASK                                                                       0x00000040L
+#define THM_GPIO_TACHIN_CTRL__RXSEL0_MASK                                                                     0x00000080L
+#define THM_GPIO_TACHIN_CTRL__RXSEL1_MASK                                                                     0x00000100L
+#define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE_MASK                                                                0x00010000L
+#define THM_GPIO_TACHIN_CTRL__OE_MASK                                                                         0x00020000L
+#define THM_GPIO_TACHIN_CTRL__A_OVERRIDE_MASK                                                                 0x00040000L
+#define THM_GPIO_TACHIN_CTRL__A_MASK                                                                          0x00080000L
+#define THM_GPIO_TACHIN_CTRL__Y_MASK                                                                          0x80000000L
+//THM_GPIO_PUMPOUT_CTRL
+#define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL__SHIFT                                                                0x0
+#define THM_GPIO_PUMPOUT_CTRL__PD__SHIFT                                                                      0x1
+#define THM_GPIO_PUMPOUT_CTRL__PU__SHIFT                                                                      0x2
+#define THM_GPIO_PUMPOUT_CTRL__SCHMEN__SHIFT                                                                  0x3
+#define THM_GPIO_PUMPOUT_CTRL__S0__SHIFT                                                                      0x4
+#define THM_GPIO_PUMPOUT_CTRL__S1__SHIFT                                                                      0x5
+#define THM_GPIO_PUMPOUT_CTRL__RXEN__SHIFT                                                                    0x6
+#define THM_GPIO_PUMPOUT_CTRL__RXSEL0__SHIFT                                                                  0x7
+#define THM_GPIO_PUMPOUT_CTRL__RXSEL1__SHIFT                                                                  0x8
+#define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE__SHIFT                                                             0x10
+#define THM_GPIO_PUMPOUT_CTRL__OE__SHIFT                                                                      0x11
+#define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE__SHIFT                                                              0x12
+#define THM_GPIO_PUMPOUT_CTRL__A__SHIFT                                                                       0x13
+#define THM_GPIO_PUMPOUT_CTRL__Y__SHIFT                                                                       0x1f
+#define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL_MASK                                                                  0x00000001L
+#define THM_GPIO_PUMPOUT_CTRL__PD_MASK                                                                        0x00000002L
+#define THM_GPIO_PUMPOUT_CTRL__PU_MASK                                                                        0x00000004L
+#define THM_GPIO_PUMPOUT_CTRL__SCHMEN_MASK                                                                    0x00000008L
+#define THM_GPIO_PUMPOUT_CTRL__S0_MASK                                                                        0x00000010L
+#define THM_GPIO_PUMPOUT_CTRL__S1_MASK                                                                        0x00000020L
+#define THM_GPIO_PUMPOUT_CTRL__RXEN_MASK                                                                      0x00000040L
+#define THM_GPIO_PUMPOUT_CTRL__RXSEL0_MASK                                                                    0x00000080L
+#define THM_GPIO_PUMPOUT_CTRL__RXSEL1_MASK                                                                    0x00000100L
+#define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE_MASK                                                               0x00010000L
+#define THM_GPIO_PUMPOUT_CTRL__OE_MASK                                                                        0x00020000L
+#define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE_MASK                                                                0x00040000L
+#define THM_GPIO_PUMPOUT_CTRL__A_MASK                                                                         0x00080000L
+#define THM_GPIO_PUMPOUT_CTRL__Y_MASK                                                                         0x80000000L
+//THM_GPIO_PUMPIN_CTRL
+#define THM_GPIO_PUMPIN_CTRL__TXIMPSEL__SHIFT                                                                 0x0
+#define THM_GPIO_PUMPIN_CTRL__PD__SHIFT                                                                       0x1
+#define THM_GPIO_PUMPIN_CTRL__PU__SHIFT                                                                       0x2
+#define THM_GPIO_PUMPIN_CTRL__SCHMEN__SHIFT                                                                   0x3
+#define THM_GPIO_PUMPIN_CTRL__S0__SHIFT                                                                       0x4
+#define THM_GPIO_PUMPIN_CTRL__S1__SHIFT                                                                       0x5
+#define THM_GPIO_PUMPIN_CTRL__RXEN__SHIFT                                                                     0x6
+#define THM_GPIO_PUMPIN_CTRL__RXSEL0__SHIFT                                                                   0x7
+#define THM_GPIO_PUMPIN_CTRL__RXSEL1__SHIFT                                                                   0x8
+#define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE__SHIFT                                                              0x10
+#define THM_GPIO_PUMPIN_CTRL__OE__SHIFT                                                                       0x11
+#define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE__SHIFT                                                               0x12
+#define THM_GPIO_PUMPIN_CTRL__A__SHIFT                                                                        0x13
+#define THM_GPIO_PUMPIN_CTRL__Y__SHIFT                                                                        0x1f
+#define THM_GPIO_PUMPIN_CTRL__TXIMPSEL_MASK                                                                   0x00000001L
+#define THM_GPIO_PUMPIN_CTRL__PD_MASK                                                                         0x00000002L
+#define THM_GPIO_PUMPIN_CTRL__PU_MASK                                                                         0x00000004L
+#define THM_GPIO_PUMPIN_CTRL__SCHMEN_MASK                                                                     0x00000008L
+#define THM_GPIO_PUMPIN_CTRL__S0_MASK                                                                         0x00000010L
+#define THM_GPIO_PUMPIN_CTRL__S1_MASK                                                                         0x00000020L
+#define THM_GPIO_PUMPIN_CTRL__RXEN_MASK                                                                       0x00000040L
+#define THM_GPIO_PUMPIN_CTRL__RXSEL0_MASK                                                                     0x00000080L
+#define THM_GPIO_PUMPIN_CTRL__RXSEL1_MASK                                                                     0x00000100L
+#define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE_MASK                                                                0x00010000L
+#define THM_GPIO_PUMPIN_CTRL__OE_MASK                                                                         0x00020000L
+#define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE_MASK                                                                 0x00040000L
+#define THM_GPIO_PUMPIN_CTRL__A_MASK                                                                          0x00080000L
+#define THM_GPIO_PUMPIN_CTRL__Y_MASK                                                                          0x80000000L
+//THM_THERMAL_INT_ENA
+#define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT                                                            0x0
+#define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT                                                            0x1
+#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT                                                         0x2
+#define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT                                                            0x3
+#define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT                                                            0x4
+#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT                                                         0x5
+#define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK                                                              0x00000001L
+#define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK                                                              0x00000002L
+#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK                                                           0x00000004L
+#define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK                                                              0x00000008L
+#define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK                                                              0x00000010L
+#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK                                                           0x00000020L
+//THM_THERMAL_INT_CTRL
+#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT                                                           0x0
+#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT                                                           0x8
+#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD__SHIFT                                                           0x10
+#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT                                                          0x18
+#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT                                                          0x19
+#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT                                                       0x1a
+#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK__SHIFT                                                       0x1b
+#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT                                                          0x1c
+#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT                                                            0x1d
+#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK                                                             0x000000FFL
+#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK                                                             0x0000FF00L
+#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD_MASK                                                             0x00FF0000L
+#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK                                                            0x01000000L
+#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK                                                            0x02000000L
+#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK                                                         0x04000000L
+#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK_MASK                                                         0x08000000L
+#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK                                                            0x10000000L
+#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK                                                              0xE0000000L
+//THM_THERMAL_INT_STATUS
+#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT                                                      0x0
+#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT                                                      0x1
+#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT                                                   0x2
+#define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT__SHIFT                                                   0x3
+#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK                                                        0x00000001L
+#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK                                                        0x00000002L
+#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK                                                     0x00000004L
+#define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT_MASK                                                     0x00000008L
+//THM_TMON0_RDIL0_DATA
+#define THM_TMON0_RDIL0_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIL0_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIL0_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIL0_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIL0_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIL1_DATA
+#define THM_TMON0_RDIL1_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIL1_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIL1_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIL1_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIL1_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIL2_DATA
+#define THM_TMON0_RDIL2_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIL2_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIL2_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIL2_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIL2_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIL3_DATA
+#define THM_TMON0_RDIL3_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIL3_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIL3_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIL3_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIL3_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIL4_DATA
+#define THM_TMON0_RDIL4_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIL4_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIL4_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIL4_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIL4_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIL5_DATA
+#define THM_TMON0_RDIL5_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIL5_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIL5_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIL5_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIL5_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIL6_DATA
+#define THM_TMON0_RDIL6_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIL6_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIL6_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIL6_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIL6_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIL7_DATA
+#define THM_TMON0_RDIL7_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIL7_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIL7_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIL7_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIL7_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIL8_DATA
+#define THM_TMON0_RDIL8_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIL8_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIL8_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIL8_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIL8_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIL9_DATA
+#define THM_TMON0_RDIL9_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIL9_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIL9_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIL9_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIL9_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIL10_DATA
+#define THM_TMON0_RDIL10_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON0_RDIL10_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON0_RDIL10_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON0_RDIL10_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON0_RDIL10_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON0_RDIL11_DATA
+#define THM_TMON0_RDIL11_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON0_RDIL11_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON0_RDIL11_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON0_RDIL11_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON0_RDIL11_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON0_RDIL12_DATA
+#define THM_TMON0_RDIL12_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON0_RDIL12_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON0_RDIL12_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON0_RDIL12_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON0_RDIL12_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON0_RDIL13_DATA
+#define THM_TMON0_RDIL13_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON0_RDIL13_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON0_RDIL13_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON0_RDIL13_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON0_RDIL13_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON0_RDIL14_DATA
+#define THM_TMON0_RDIL14_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON0_RDIL14_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON0_RDIL14_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON0_RDIL14_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON0_RDIL14_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON0_RDIL15_DATA
+#define THM_TMON0_RDIL15_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON0_RDIL15_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON0_RDIL15_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON0_RDIL15_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON0_RDIL15_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON0_RDIR0_DATA
+#define THM_TMON0_RDIR0_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIR0_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIR0_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIR0_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIR0_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIR1_DATA
+#define THM_TMON0_RDIR1_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIR1_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIR1_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIR1_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIR1_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIR2_DATA
+#define THM_TMON0_RDIR2_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIR2_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIR2_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIR2_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIR2_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIR3_DATA
+#define THM_TMON0_RDIR3_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIR3_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIR3_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIR3_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIR3_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIR4_DATA
+#define THM_TMON0_RDIR4_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIR4_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIR4_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIR4_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIR4_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIR5_DATA
+#define THM_TMON0_RDIR5_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIR5_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIR5_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIR5_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIR5_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIR6_DATA
+#define THM_TMON0_RDIR6_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIR6_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIR6_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIR6_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIR6_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIR7_DATA
+#define THM_TMON0_RDIR7_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIR7_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIR7_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIR7_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIR7_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIR8_DATA
+#define THM_TMON0_RDIR8_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIR8_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIR8_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIR8_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIR8_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIR9_DATA
+#define THM_TMON0_RDIR9_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON0_RDIR9_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON0_RDIR9_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON0_RDIR9_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON0_RDIR9_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON0_RDIR10_DATA
+#define THM_TMON0_RDIR10_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON0_RDIR10_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON0_RDIR10_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON0_RDIR10_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON0_RDIR10_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON0_RDIR11_DATA
+#define THM_TMON0_RDIR11_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON0_RDIR11_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON0_RDIR11_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON0_RDIR11_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON0_RDIR11_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON0_RDIR12_DATA
+#define THM_TMON0_RDIR12_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON0_RDIR12_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON0_RDIR12_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON0_RDIR12_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON0_RDIR12_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON0_RDIR13_DATA
+#define THM_TMON0_RDIR13_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON0_RDIR13_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON0_RDIR13_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON0_RDIR13_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON0_RDIR13_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON0_RDIR14_DATA
+#define THM_TMON0_RDIR14_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON0_RDIR14_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON0_RDIR14_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON0_RDIR14_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON0_RDIR14_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON0_RDIR15_DATA
+#define THM_TMON0_RDIR15_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON0_RDIR15_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON0_RDIR15_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON0_RDIR15_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON0_RDIR15_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON0_INT_DATA
+#define THM_TMON0_INT_DATA__Z__SHIFT                                                                          0x0
+#define THM_TMON0_INT_DATA__VALID__SHIFT                                                                      0xb
+#define THM_TMON0_INT_DATA__TEMP__SHIFT                                                                       0xc
+#define THM_TMON0_INT_DATA__Z_MASK                                                                            0x000007FFL
+#define THM_TMON0_INT_DATA__VALID_MASK                                                                        0x00000800L
+#define THM_TMON0_INT_DATA__TEMP_MASK                                                                         0x00FFF000L
+//THM_TMON0_DEBUG
+#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT                                                                     0x0
+#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT                                                                       0x5
+#define THM_TMON0_DEBUG__DEBUG_RDI_MASK                                                                       0x0000001FL
+#define THM_TMON0_DEBUG__DEBUG_Z_MASK                                                                         0x0000FFE0L
+//THM_TMON1_RDIL0_DATA
+#define THM_TMON1_RDIL0_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIL0_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIL0_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIL0_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIL0_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIL1_DATA
+#define THM_TMON1_RDIL1_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIL1_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIL1_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIL1_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIL1_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIL2_DATA
+#define THM_TMON1_RDIL2_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIL2_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIL2_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIL2_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIL2_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIL3_DATA
+#define THM_TMON1_RDIL3_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIL3_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIL3_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIL3_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIL3_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIL4_DATA
+#define THM_TMON1_RDIL4_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIL4_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIL4_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIL4_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIL4_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIL5_DATA
+#define THM_TMON1_RDIL5_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIL5_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIL5_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIL5_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIL5_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIL6_DATA
+#define THM_TMON1_RDIL6_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIL6_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIL6_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIL6_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIL6_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIL7_DATA
+#define THM_TMON1_RDIL7_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIL7_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIL7_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIL7_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIL7_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIL8_DATA
+#define THM_TMON1_RDIL8_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIL8_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIL8_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIL8_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIL8_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIL9_DATA
+#define THM_TMON1_RDIL9_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIL9_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIL9_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIL9_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIL9_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIL10_DATA
+#define THM_TMON1_RDIL10_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON1_RDIL10_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON1_RDIL10_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON1_RDIL10_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON1_RDIL10_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON1_RDIL11_DATA
+#define THM_TMON1_RDIL11_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON1_RDIL11_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON1_RDIL11_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON1_RDIL11_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON1_RDIL11_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON1_RDIL12_DATA
+#define THM_TMON1_RDIL12_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON1_RDIL12_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON1_RDIL12_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON1_RDIL12_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON1_RDIL12_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON1_RDIL13_DATA
+#define THM_TMON1_RDIL13_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON1_RDIL13_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON1_RDIL13_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON1_RDIL13_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON1_RDIL13_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON1_RDIL14_DATA
+#define THM_TMON1_RDIL14_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON1_RDIL14_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON1_RDIL14_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON1_RDIL14_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON1_RDIL14_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON1_RDIL15_DATA
+#define THM_TMON1_RDIL15_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON1_RDIL15_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON1_RDIL15_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON1_RDIL15_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON1_RDIL15_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON1_RDIR0_DATA
+#define THM_TMON1_RDIR0_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIR0_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIR0_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIR0_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIR0_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIR1_DATA
+#define THM_TMON1_RDIR1_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIR1_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIR1_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIR1_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIR1_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIR2_DATA
+#define THM_TMON1_RDIR2_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIR2_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIR2_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIR2_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIR2_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIR3_DATA
+#define THM_TMON1_RDIR3_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIR3_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIR3_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIR3_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIR3_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIR4_DATA
+#define THM_TMON1_RDIR4_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIR4_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIR4_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIR4_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIR4_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIR5_DATA
+#define THM_TMON1_RDIR5_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIR5_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIR5_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIR5_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIR5_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIR6_DATA
+#define THM_TMON1_RDIR6_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIR6_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIR6_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIR6_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIR6_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIR7_DATA
+#define THM_TMON1_RDIR7_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIR7_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIR7_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIR7_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIR7_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIR8_DATA
+#define THM_TMON1_RDIR8_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIR8_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIR8_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIR8_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIR8_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIR9_DATA
+#define THM_TMON1_RDIR9_DATA__Z__SHIFT                                                                        0x0
+#define THM_TMON1_RDIR9_DATA__VALID__SHIFT                                                                    0xb
+#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT                                                                     0xc
+#define THM_TMON1_RDIR9_DATA__Z_MASK                                                                          0x000007FFL
+#define THM_TMON1_RDIR9_DATA__VALID_MASK                                                                      0x00000800L
+#define THM_TMON1_RDIR9_DATA__TEMP_MASK                                                                       0x00FFF000L
+//THM_TMON1_RDIR10_DATA
+#define THM_TMON1_RDIR10_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON1_RDIR10_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON1_RDIR10_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON1_RDIR10_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON1_RDIR10_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON1_RDIR11_DATA
+#define THM_TMON1_RDIR11_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON1_RDIR11_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON1_RDIR11_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON1_RDIR11_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON1_RDIR11_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON1_RDIR12_DATA
+#define THM_TMON1_RDIR12_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON1_RDIR12_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON1_RDIR12_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON1_RDIR12_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON1_RDIR12_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON1_RDIR13_DATA
+#define THM_TMON1_RDIR13_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON1_RDIR13_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON1_RDIR13_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON1_RDIR13_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON1_RDIR13_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON1_RDIR14_DATA
+#define THM_TMON1_RDIR14_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON1_RDIR14_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON1_RDIR14_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON1_RDIR14_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON1_RDIR14_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON1_RDIR15_DATA
+#define THM_TMON1_RDIR15_DATA__Z__SHIFT                                                                       0x0
+#define THM_TMON1_RDIR15_DATA__VALID__SHIFT                                                                   0xb
+#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT                                                                    0xc
+#define THM_TMON1_RDIR15_DATA__Z_MASK                                                                         0x000007FFL
+#define THM_TMON1_RDIR15_DATA__VALID_MASK                                                                     0x00000800L
+#define THM_TMON1_RDIR15_DATA__TEMP_MASK                                                                      0x00FFF000L
+//THM_TMON1_INT_DATA
+#define THM_TMON1_INT_DATA__Z__SHIFT                                                                          0x0
+#define THM_TMON1_INT_DATA__VALID__SHIFT                                                                      0xb
+#define THM_TMON1_INT_DATA__TEMP__SHIFT                                                                       0xc
+#define THM_TMON1_INT_DATA__Z_MASK                                                                            0x000007FFL
+#define THM_TMON1_INT_DATA__VALID_MASK                                                                        0x00000800L
+#define THM_TMON1_INT_DATA__TEMP_MASK                                                                         0x00FFF000L
+//THM_TMON1_DEBUG
+#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT                                                                     0x0
+#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT                                                                       0x5
+#define THM_TMON1_DEBUG__DEBUG_RDI_MASK                                                                       0x0000001FL
+#define THM_TMON1_DEBUG__DEBUG_Z_MASK                                                                         0x0000FFE0L
+//THM_DIE1_TEMP
+#define THM_DIE1_TEMP__TEMP__SHIFT                                                                            0x0
+#define THM_DIE1_TEMP__VALID__SHIFT                                                                           0xb
+#define THM_DIE1_TEMP__TEMP_MASK                                                                              0x000007FFL
+#define THM_DIE1_TEMP__VALID_MASK                                                                             0x00000800L
+//THM_DIE2_TEMP
+#define THM_DIE2_TEMP__TEMP__SHIFT                                                                            0x0
+#define THM_DIE2_TEMP__VALID__SHIFT                                                                           0xb
+#define THM_DIE2_TEMP__TEMP_MASK                                                                              0x000007FFL
+#define THM_DIE2_TEMP__VALID_MASK                                                                             0x00000800L
+//THM_DIE3_TEMP
+#define THM_DIE3_TEMP__TEMP__SHIFT                                                                            0x0
+#define THM_DIE3_TEMP__VALID__SHIFT                                                                           0xb
+#define THM_DIE3_TEMP__TEMP_MASK                                                                              0x000007FFL
+#define THM_DIE3_TEMP__VALID_MASK                                                                             0x00000800L
+//CG_MULT_THERMAL_CTRL
+#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT                                                                0x0
+#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT                                                                   0x4
+#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT                                                        0x9
+#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT                                                                 0x14
+#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK                                                                  0x0000000FL
+#define CG_MULT_THERMAL_CTRL__UNUSED_MASK                                                                     0x000001F0L
+#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK                                                          0x00000200L
+#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK                                                                   0x0FF00000L
+//CG_MULT_THERMAL_STATUS
+#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT                                                          0x0
+#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT                                                               0x9
+#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK                                                            0x000001FFL
+#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK                                                                 0x0003FE00L
+//THM_TMON0_COEFF
+#define THM_TMON0_COEFF__C_OFFSET__SHIFT                                                                      0x0
+#define THM_TMON0_COEFF__D__SHIFT                                                                             0xb
+#define THM_TMON0_COEFF__C_OFFSET_MASK                                                                        0x000007FFL
+#define THM_TMON0_COEFF__D_MASK                                                                               0x0003F800L
+//THM_TMON1_COEFF
+#define THM_TMON1_COEFF__C_OFFSET__SHIFT                                                                      0x0
+#define THM_TMON1_COEFF__D__SHIFT                                                                             0xb
+#define THM_TMON1_COEFF__C_OFFSET_MASK                                                                        0x000007FFL
+#define THM_TMON1_COEFF__D_MASK                                                                               0x0003F800L
+//CG_FDO_CTRL0
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT                                                                  0x0
+#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT                                                                  0x8
+#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT                                                                   0x10
+#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT                                                                   0x11
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT                                                                  0x17
+#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT                                                                     0x18
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK                                                                    0x000000FFL
+#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK                                                                    0x0000FF00L
+#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK                                                                     0x00010000L
+#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK                                                                     0x007E0000L
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK                                                                    0x00800000L
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK                                                                       0xFF000000L
+//CG_FDO_CTRL1
+#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT                                                                     0x0
+#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT                                                                        0x8
+#define CG_FDO_CTRL1__M__SHIFT                                                                                0x10
+#define CG_FDO_CTRL1__RESERVED__SHIFT                                                                         0x18
+#define CG_FDO_CTRL1__FMAX_DUTY100_MASK                                                                       0x000000FFL
+#define CG_FDO_CTRL1__FMIN_DUTY_MASK                                                                          0x0000FF00L
+#define CG_FDO_CTRL1__M_MASK                                                                                  0x00FF0000L
+#define CG_FDO_CTRL1__RESERVED_MASK                                                                           0x3F000000L
+//CG_FDO_CTRL2
+#define CG_FDO_CTRL2__TMIN__SHIFT                                                                             0x0
+#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT                                                                  0x8
+#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT                                                                     0xb
+#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT                                                                      0xe
+#define CG_FDO_CTRL2__TMAX__SHIFT                                                                             0x11
+#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT                                                               0x19
+#define CG_FDO_CTRL2__TMIN_MASK                                                                               0x000000FFL
+#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK                                                                    0x00000700L
+#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK                                                                       0x00003800L
+#define CG_FDO_CTRL2__TMIN_HYSTER_MASK                                                                        0x0001C000L
+#define CG_FDO_CTRL2__TMAX_MASK                                                                               0x01FE0000L
+#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK                                                                 0xFE000000L
+//CG_TACH_CTRL
+#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT                                                                     0x0
+#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT                                                                    0x3
+#define CG_TACH_CTRL__EDGE_PER_REV_MASK                                                                       0x00000007L
+#define CG_TACH_CTRL__TARGET_PERIOD_MASK                                                                      0xFFFFFFF8L
+//CG_TACH_STATUS
+#define CG_TACH_STATUS__TACH_PERIOD__SHIFT                                                                    0x0
+#define CG_TACH_STATUS__TACH_PERIOD_MASK                                                                      0xFFFFFFFFL
+//CG_THERMAL_STATUS
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT                                                                0x9
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK                                                                  0x0001FE00L
+//CG_PUMP_CTRL0
+#define CG_PUMP_CTRL0__PUMP_STATIC_DUTY__SHIFT                                                                0x0
+#define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY__SHIFT                                                                0x8
+#define CG_PUMP_CTRL0__PUMP_PWM_MANUAL__SHIFT                                                                 0x10
+#define CG_PUMP_CTRL0__PUMP_PWM_HYSTER__SHIFT                                                                 0x11
+#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN__SHIFT                                                                0x17
+#define CG_PUMP_CTRL0__PUMP_PWM_RAMP__SHIFT                                                                   0x18
+#define CG_PUMP_CTRL0__PUMP_STATIC_DUTY_MASK                                                                  0x000000FFL
+#define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY_MASK                                                                  0x0000FF00L
+#define CG_PUMP_CTRL0__PUMP_PWM_MANUAL_MASK                                                                   0x00010000L
+#define CG_PUMP_CTRL0__PUMP_PWM_HYSTER_MASK                                                                   0x007E0000L
+#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN_MASK                                                                  0x00800000L
+#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_MASK                                                                     0xFF000000L
+//CG_PUMP_CTRL1
+#define CG_PUMP_CTRL1__PMAX_DUTY100__SHIFT                                                                    0x0
+#define CG_PUMP_CTRL1__PMIN_DUTY__SHIFT                                                                       0x8
+#define CG_PUMP_CTRL1__M__SHIFT                                                                               0x10
+#define CG_PUMP_CTRL1__RESERVED__SHIFT                                                                        0x18
+#define CG_PUMP_CTRL1__PMAX_DUTY100_MASK                                                                      0x000000FFL
+#define CG_PUMP_CTRL1__PMIN_DUTY_MASK                                                                         0x0000FF00L
+#define CG_PUMP_CTRL1__M_MASK                                                                                 0x00FF0000L
+#define CG_PUMP_CTRL1__RESERVED_MASK                                                                          0x3F000000L
+//CG_PUMP_CTRL2
+#define CG_PUMP_CTRL2__TMIN__SHIFT                                                                            0x0
+#define CG_PUMP_CTRL2__PUMP_SPINUP_TIME__SHIFT                                                                0x8
+#define CG_PUMP_CTRL2__PUMP_PWM_MODE__SHIFT                                                                   0xb
+#define CG_PUMP_CTRL2__TMIN_HYSTER__SHIFT                                                                     0xe
+#define CG_PUMP_CTRL2__TMAX__SHIFT                                                                            0x11
+#define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE__SHIFT                                                              0x19
+#define CG_PUMP_CTRL2__TMIN_MASK                                                                              0x000000FFL
+#define CG_PUMP_CTRL2__PUMP_SPINUP_TIME_MASK                                                                  0x00000700L
+#define CG_PUMP_CTRL2__PUMP_PWM_MODE_MASK                                                                     0x00003800L
+#define CG_PUMP_CTRL2__TMIN_HYSTER_MASK                                                                       0x0001C000L
+#define CG_PUMP_CTRL2__TMAX_MASK                                                                              0x01FE0000L
+#define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE_MASK                                                                0xFE000000L
+//CG_PUMP_TACH_CTRL
+#define CG_PUMP_TACH_CTRL__EDGE_PER_REV__SHIFT                                                                0x0
+#define CG_PUMP_TACH_CTRL__TARGET_PERIOD__SHIFT                                                               0x3
+#define CG_PUMP_TACH_CTRL__EDGE_PER_REV_MASK                                                                  0x00000007L
+#define CG_PUMP_TACH_CTRL__TARGET_PERIOD_MASK                                                                 0xFFFFFFF8L
+//CG_PUMP_TACH_STATUS
+#define CG_PUMP_TACH_STATUS__TACH_PERIOD__SHIFT                                                               0x0
+#define CG_PUMP_TACH_STATUS__TACH_PERIOD_MASK                                                                 0xFFFFFFFFL
+//CG_PUMP_STATUS
+#define CG_PUMP_STATUS__PUMP_PWM_DUTY__SHIFT                                                                  0x9
+#define CG_PUMP_STATUS__PUMP_PWM_DUTY_MASK                                                                    0x0001FE00L
+//THM_TCON_LOCAL0
+#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT                                                               0x1
+#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT                                                               0x2
+#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK                                                                 0x00000002L
+#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK                                                                 0x00000004L
+//THM_TCON_LOCAL1
+#define THM_TCON_LOCAL1__Turn_Off_TMON0__SHIFT                                                                0x0
+#define THM_TCON_LOCAL1__Turn_Off_TMON1__SHIFT                                                                0x1
+#define THM_TCON_LOCAL1__PowerDownTmon0__SHIFT                                                                0x4
+#define THM_TCON_LOCAL1__PowerDownTmon1__SHIFT                                                                0x5
+#define THM_TCON_LOCAL1__Turn_Off_TMON0_MASK                                                                  0x00000001L
+#define THM_TCON_LOCAL1__Turn_Off_TMON1_MASK                                                                  0x00000002L
+#define THM_TCON_LOCAL1__PowerDownTmon0_MASK                                                                  0x00000010L
+#define THM_TCON_LOCAL1__PowerDownTmon1_MASK                                                                  0x00000020L
+//THM_TCON_LOCAL2
+#define THM_TCON_LOCAL2__TMON_init_delay__SHIFT                                                               0x0
+#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time__SHIFT                                                       0x2
+#define THM_TCON_LOCAL2__short_stagger_count__SHIFT                                                           0x5
+#define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT                                                           0x6
+#define THM_TCON_LOCAL2__temp_read_skip_scale__SHIFT                                                          0xa
+#define THM_TCON_LOCAL2__skip_scale_correction__SHIFT                                                         0xb
+#define THM_TCON_LOCAL2__TMON_init_delay_MASK                                                                 0x00000003L
+#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time_MASK                                                         0x0000000CL
+#define THM_TCON_LOCAL2__short_stagger_count_MASK                                                             0x00000020L
+#define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK                                                             0x00000040L
+#define THM_TCON_LOCAL2__temp_read_skip_scale_MASK                                                            0x00000400L
+#define THM_TCON_LOCAL2__skip_scale_correction_MASK                                                           0x00000800L
+//THM_TCON_LOCAL3
+#define THM_TCON_LOCAL3__Global_TMAX__SHIFT                                                                   0x0
+#define THM_TCON_LOCAL3__Global_TMAX_MASK                                                                     0x000007FFL
+//THM_TCON_LOCAL4
+#define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT                                                                0x0
+#define THM_TCON_LOCAL4__Global_TMAX_ID_MASK                                                                  0x000000FFL
+//THM_TCON_LOCAL5
+#define THM_TCON_LOCAL5__Global_TMIN__SHIFT                                                                   0x0
+#define THM_TCON_LOCAL5__Global_TMIN_MASK                                                                     0x000007FFL
+//THM_TCON_LOCAL6
+#define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT                                                                0x0
+#define THM_TCON_LOCAL6__Global_TMIN_ID_MASK                                                                  0x000000FFL
+//THM_TCON_LOCAL7
+#define THM_TCON_LOCAL7__THERMID__SHIFT                                                                       0x0
+#define THM_TCON_LOCAL7__THERMID_MASK                                                                         0x000000FFL
+//THM_TCON_LOCAL8
+#define THM_TCON_LOCAL8__THERMMAX__SHIFT                                                                      0x0
+#define THM_TCON_LOCAL8__THERMMAX_MASK                                                                        0x000007FFL
+//THM_TCON_LOCAL9
+#define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT                                                                  0x0
+#define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK                                                                    0x000007FFL
+//THM_TCON_LOCAL10
+#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT                                                           0x0
+#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK                                                             0x000000FFL
+//THM_TCON_LOCAL11
+#define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT                                                                 0x0
+#define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK                                                                   0x000007FFL
+//THM_TCON_LOCAL12
+#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT                                                           0x0
+#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK                                                             0x000000FFL
+//THM_TCON_LOCAL13
+#define THM_TCON_LOCAL13__boot_done__SHIFT                                                                    0x0
+#define THM_TCON_LOCAL13__boot_done_MASK                                                                      0x00000001L
+//THM_BACO_CNTL
+#define THM_BACO_CNTL__BACO_MODE__SHIFT                                                                       0x0
+#define THM_BACO_CNTL__BACO_ISO_EN__SHIFT                                                                     0x1
+#define THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT                                                              0x2
+#define THM_BACO_CNTL__BACO_RESET_EN__SHIFT                                                                   0x3
+#define THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT                                                             0x4
+#define THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT                                                                 0x5
+#define THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT                                                             0x6
+#define THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT                                                                 0x7
+#define THM_BACO_CNTL__BACO_EXIT__SHIFT                                                                       0x8
+#define THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT                                                                 0x9
+#define THM_BACO_CNTL__BACO_SB_AXI_FENCE__SHIFT                                                               0x1e
+#define THM_BACO_CNTL__SOC_DOMAIN_IDLE__SHIFT                                                                 0x1f
+#define THM_BACO_CNTL__BACO_MODE_MASK                                                                         0x00000001L
+#define THM_BACO_CNTL__BACO_ISO_EN_MASK                                                                       0x00000002L
+#define THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK                                                                0x00000004L
+#define THM_BACO_CNTL__BACO_RESET_EN_MASK                                                                     0x00000008L
+#define THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK                                                               0x00000010L
+#define THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK                                                                   0x00000020L
+#define THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK                                                               0x00000040L
+#define THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK                                                                   0x00000080L
+#define THM_BACO_CNTL__BACO_EXIT_MASK                                                                         0x00000100L
+#define THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK                                                                   0x00000200L
+#define THM_BACO_CNTL__BACO_SB_AXI_FENCE_MASK                                                                 0x40000000L
+#define THM_BACO_CNTL__SOC_DOMAIN_IDLE_MASK                                                                   0x80000000L
+//THM_BACO_TIMING0
+#define THM_BACO_TIMING0__BACO_ISO_EXIT_CNT__SHIFT                                                            0x0
+#define THM_BACO_TIMING0__BACO_PWROKRAW_EXIT_CNT__SHIFT                                                       0x8
+#define THM_BACO_TIMING0__BACO_RESET_EXIT_CNT__SHIFT                                                          0x10
+#define THM_BACO_TIMING0__BACO_VDCI_RESET_EXIT_CNT__SHIFT                                                     0x18
+#define THM_BACO_TIMING0__BACO_ISO_EXIT_CNT_MASK                                                              0x000000FFL
+#define THM_BACO_TIMING0__BACO_PWROKRAW_EXIT_CNT_MASK                                                         0x0000FF00L
+#define THM_BACO_TIMING0__BACO_RESET_EXIT_CNT_MASK                                                            0x00FF0000L
+#define THM_BACO_TIMING0__BACO_VDCI_RESET_EXIT_CNT_MASK                                                       0xFF000000L
+//THM_BACO_TIMING1
+#define THM_BACO_TIMING1__BACO_SMNCLK_EXIT_CNT__SHIFT                                                         0x0
+#define THM_BACO_TIMING1__BACO_FENCE_EXIT_CNT__SHIFT                                                          0x8
+#define THM_BACO_TIMING1__BACO_REFCLK_EXIT_CNT__SHIFT                                                         0x10
+#define THM_BACO_TIMING1__BACO_MODE_EXIT_CNT__SHIFT                                                           0x18
+#define THM_BACO_TIMING1__BACO_SMNCLK_EXIT_CNT_MASK                                                           0x000000FFL
+#define THM_BACO_TIMING1__BACO_FENCE_EXIT_CNT_MASK                                                            0x0000FF00L
+#define THM_BACO_TIMING1__BACO_REFCLK_EXIT_CNT_MASK                                                           0x00FF0000L
+#define THM_BACO_TIMING1__BACO_MODE_EXIT_CNT_MASK                                                             0xFF000000L
+//XTAL_CNTL
+#define XTAL_CNTL__PCIE_REFCLK_SWITCH__SHIFT                                                                  0x0
+#define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN__SHIFT                                                              0x4
+#define XTAL_CNTL__CORE_XTAL_PWDN__SHIFT                                                                      0x8
+#define XTAL_CNTL__OSC_GAIN_EN__SHIFT                                                                         0xc
+#define XTAL_CNTL__PCIE_REFCLK_SWITCH_MASK                                                                    0x00000001L
+#define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN_MASK                                                                0x00000010L
+#define XTAL_CNTL__CORE_XTAL_PWDN_MASK                                                                        0x00000100L
+#define XTAL_CNTL__OSC_GAIN_EN_MASK                                                                           0x00007000L
+//SBTSI_REMOTE_TEMP
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensor__SHIFT                                                            0x0
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId__SHIFT                                                          0xb
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid__SHIFT                                                       0x13
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensor_MASK                                                              0x000007FFL
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId_MASK                                                            0x0007F800L
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid_MASK                                                         0x00080000L
+//SBRMI_CONTROL
+#define SBRMI_CONTROL__READ_CMD_INT_DIS__SHIFT                                                                0x0
+#define SBRMI_CONTROL__DPD__SHIFT                                                                             0x1
+#define SBRMI_CONTROL__DbrdySts__SHIFT                                                                        0x2
+#define SBRMI_CONTROL__READ_CMD_INT_DIS_MASK                                                                  0x00000001L
+#define SBRMI_CONTROL__DPD_MASK                                                                               0x00000002L
+#define SBRMI_CONTROL__DbrdySts_MASK                                                                          0x00000004L
+//SBRMI_COMMAND
+#define SBRMI_COMMAND__Command__SHIFT                                                                         0x0
+#define SBRMI_COMMAND__WrDataLen__SHIFT                                                                       0x8
+#define SBRMI_COMMAND__RdDataLen__SHIFT                                                                       0x10
+#define SBRMI_COMMAND__CommandSent__SHIFT                                                                     0x18
+#define SBRMI_COMMAND__CommandNotSupported__SHIFT                                                             0x19
+#define SBRMI_COMMAND__CommandAborted__SHIFT                                                                  0x1a
+#define SBRMI_COMMAND__Status__SHIFT                                                                          0x1c
+#define SBRMI_COMMAND__Command_MASK                                                                           0x000000FFL
+#define SBRMI_COMMAND__WrDataLen_MASK                                                                         0x0000FF00L
+#define SBRMI_COMMAND__RdDataLen_MASK                                                                         0x00FF0000L
+#define SBRMI_COMMAND__CommandSent_MASK                                                                       0x01000000L
+#define SBRMI_COMMAND__CommandNotSupported_MASK                                                               0x02000000L
+#define SBRMI_COMMAND__CommandAborted_MASK                                                                    0x04000000L
+#define SBRMI_COMMAND__Status_MASK                                                                            0xF0000000L
+//SBRMI_WRITE_DATA0
+#define SBRMI_WRITE_DATA0__WrByte0__SHIFT                                                                     0x0
+#define SBRMI_WRITE_DATA0__WrByte1__SHIFT                                                                     0x8
+#define SBRMI_WRITE_DATA0__WrByte2__SHIFT                                                                     0x10
+#define SBRMI_WRITE_DATA0__WrByte3__SHIFT                                                                     0x18
+#define SBRMI_WRITE_DATA0__WrByte0_MASK                                                                       0x000000FFL
+#define SBRMI_WRITE_DATA0__WrByte1_MASK                                                                       0x0000FF00L
+#define SBRMI_WRITE_DATA0__WrByte2_MASK                                                                       0x00FF0000L
+#define SBRMI_WRITE_DATA0__WrByte3_MASK                                                                       0xFF000000L
+//SBRMI_WRITE_DATA1
+#define SBRMI_WRITE_DATA1__WrByte4__SHIFT                                                                     0x0
+#define SBRMI_WRITE_DATA1__WrByte5__SHIFT                                                                     0x8
+#define SBRMI_WRITE_DATA1__WrByte6__SHIFT                                                                     0x10
+#define SBRMI_WRITE_DATA1__WrByte7__SHIFT                                                                     0x18
+#define SBRMI_WRITE_DATA1__WrByte4_MASK                                                                       0x000000FFL
+#define SBRMI_WRITE_DATA1__WrByte5_MASK                                                                       0x0000FF00L
+#define SBRMI_WRITE_DATA1__WrByte6_MASK                                                                       0x00FF0000L
+#define SBRMI_WRITE_DATA1__WrByte7_MASK                                                                       0xFF000000L
+//SBRMI_WRITE_DATA2
+#define SBRMI_WRITE_DATA2__WrByte8__SHIFT                                                                     0x0
+#define SBRMI_WRITE_DATA2__WrByte9__SHIFT                                                                     0x8
+#define SBRMI_WRITE_DATA2__WrByte10__SHIFT                                                                    0x10
+#define SBRMI_WRITE_DATA2__WrByte11__SHIFT                                                                    0x18
+#define SBRMI_WRITE_DATA2__WrByte8_MASK                                                                       0x000000FFL
+#define SBRMI_WRITE_DATA2__WrByte9_MASK                                                                       0x0000FF00L
+#define SBRMI_WRITE_DATA2__WrByte10_MASK                                                                      0x00FF0000L
+#define SBRMI_WRITE_DATA2__WrByte11_MASK                                                                      0xFF000000L
+//SBRMI_READ_DATA0
+#define SBRMI_READ_DATA0__RdByte0__SHIFT                                                                      0x0
+#define SBRMI_READ_DATA0__RdByte1__SHIFT                                                                      0x8
+#define SBRMI_READ_DATA0__RdByte2__SHIFT                                                                      0x10
+#define SBRMI_READ_DATA0__RdByte3__SHIFT                                                                      0x18
+#define SBRMI_READ_DATA0__RdByte0_MASK                                                                        0x000000FFL
+#define SBRMI_READ_DATA0__RdByte1_MASK                                                                        0x0000FF00L
+#define SBRMI_READ_DATA0__RdByte2_MASK                                                                        0x00FF0000L
+#define SBRMI_READ_DATA0__RdByte3_MASK                                                                        0xFF000000L
+//SBRMI_READ_DATA1
+#define SBRMI_READ_DATA1__RdByte4__SHIFT                                                                      0x0
+#define SBRMI_READ_DATA1__RdByte5__SHIFT                                                                      0x8
+#define SBRMI_READ_DATA1__RdByte6__SHIFT                                                                      0x10
+#define SBRMI_READ_DATA1__RdByte7__SHIFT                                                                      0x18
+#define SBRMI_READ_DATA1__RdByte4_MASK                                                                        0x000000FFL
+#define SBRMI_READ_DATA1__RdByte5_MASK                                                                        0x0000FF00L
+#define SBRMI_READ_DATA1__RdByte6_MASK                                                                        0x00FF0000L
+#define SBRMI_READ_DATA1__RdByte7_MASK                                                                        0xFF000000L
+//SBRMI_CORE_EN_NUMBER
+#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum__SHIFT                                                           0x0
+#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum_MASK                                                             0x0000007FL
+//SBRMI_CORE_EN_STATUS0
+#define SBRMI_CORE_EN_STATUS0__CoreEnStat0__SHIFT                                                             0x0
+#define SBRMI_CORE_EN_STATUS0__CoreEnStat0_MASK                                                               0xFFFFFFFFL
+//SBRMI_CORE_EN_STATUS1
+#define SBRMI_CORE_EN_STATUS1__CoreEnStat1__SHIFT                                                             0x0
+#define SBRMI_CORE_EN_STATUS1__CoreEnStat1_MASK                                                               0xFFFFFFFFL
+//SBRMI_APIC_STATUS0
+#define SBRMI_APIC_STATUS0__APICStat0__SHIFT                                                                  0x0
+#define SBRMI_APIC_STATUS0__APICStat0_MASK                                                                    0xFFFFFFFFL
+//SBRMI_APIC_STATUS1
+#define SBRMI_APIC_STATUS1__APICStat1__SHIFT                                                                  0x0
+#define SBRMI_APIC_STATUS1__APICStat1_MASK                                                                    0xFFFFFFFFL
+//SBRMI_MCE_STATUS0
+#define SBRMI_MCE_STATUS0__MceStat0__SHIFT                                                                    0x0
+#define SBRMI_MCE_STATUS0__MceStat0_MASK                                                                      0xFFFFFFFFL
+//SBRMI_MCE_STATUS1
+#define SBRMI_MCE_STATUS1__MceStat1__SHIFT                                                                    0x0
+#define SBRMI_MCE_STATUS1__MceStat1_MASK                                                                      0xFFFFFFFFL
+//SMBUS_CNTL0
+#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE__SHIFT                                                     0x0
+#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR__SHIFT                                                              0x1
+#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE__SHIFT                                                                0x8
+#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES__SHIFT                                                          0x10
+#define SMBUS_CNTL0__THM_READY__SHIFT                                                                         0x14
+#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE_MASK                                                       0x00000001L
+#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_MASK                                                                0x000000FEL
+#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE_MASK                                                                  0x0000FF00L
+#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES_MASK                                                            0x00070000L
+#define SMBUS_CNTL0__THM_READY_MASK                                                                           0x00100000L
+//SMBUS_CNTL1
+#define SMBUS_CNTL1__SMB_TIMEOUT_EN__SHIFT                                                                    0x0
+#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN__SHIFT                                                                 0x1
+#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN__SHIFT                                                                 0x9
+#define SMBUS_CNTL1__SMB_TIMEOUT_EN_MASK                                                                      0x00000001L
+#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN_MASK                                                                   0x000001FEL
+#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN_MASK                                                                   0x0001FE00L
+//SMBUS_BLKWR_CMD_CTRL0
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0__SHIFT                                                         0x0
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1__SHIFT                                                         0x8
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2__SHIFT                                                         0x10
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3__SHIFT                                                         0x18
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0_MASK                                                           0x000000FFL
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1_MASK                                                           0x0000FF00L
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2_MASK                                                           0x00FF0000L
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3_MASK                                                           0xFF000000L
+//SMBUS_BLKWR_CMD_CTRL1
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4__SHIFT                                                         0x0
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5__SHIFT                                                         0x8
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6__SHIFT                                                         0x10
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7__SHIFT                                                         0x18
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4_MASK                                                           0x000000FFL
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5_MASK                                                           0x0000FF00L
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6_MASK                                                           0x00FF0000L
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7_MASK                                                           0xFF000000L
+//SMBUS_BLKRD_CMD_CTRL0
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0__SHIFT                                                         0x0
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1__SHIFT                                                         0x8
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2__SHIFT                                                         0x10
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3__SHIFT                                                         0x18
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0_MASK                                                           0x000000FFL
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1_MASK                                                           0x0000FF00L
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2_MASK                                                           0x00FF0000L
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3_MASK                                                           0xFF000000L
+//SMBUS_BLKRD_CMD_CTRL1
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4__SHIFT                                                         0x0
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5__SHIFT                                                         0x8
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6__SHIFT                                                         0x10
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7__SHIFT                                                         0x18
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4_MASK                                                           0x000000FFL
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5_MASK                                                           0x0000FF00L
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6_MASK                                                           0x00FF0000L
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7_MASK                                                           0xFF000000L
+//SMBUS_TIMING_CNTL0
+#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN__SHIFT                                                         0x0
+#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN__SHIFT                                            0x16
+#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN_MASK                                                           0x003FFFFFL
+#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN_MASK                                              0x3FC00000L
+//SMBUS_TIMING_CNTL1
+#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN__SHIFT                                                  0x0
+#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT                                                   0x5
+#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN__SHIFT                                           0xb
+#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN__SHIFT                                                        0x14
+#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN_MASK                                                    0x0000001FL
+#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK                                                     0x000007E0L
+#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN_MASK                                             0x000FF800L
+#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN_MASK                                                          0x3FF00000L
+//SMBUS_TIMING_CNTL2
+#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN__SHIFT                                                  0x0
+#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN__SHIFT                                                   0xd
+#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN_MASK                                                    0x00001FFFL
+#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN_MASK                                                     0x07FFE000L
+//SMBUS_TRIGGER_CNTL
+#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER__SHIFT                                                     0x0
+#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER__SHIFT                                                     0x8
+#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER_MASK                                                       0x00000001L
+#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER_MASK                                                       0x00000100L
+//SMBUS_UDID_CNTL0
+#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED__SHIFT                                                            0x0
+#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN__SHIFT                                                       0x1f
+#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED_MASK                                                              0x7FFFFFFFL
+#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN_MASK                                                         0x80000000L
+//SMBUS_UDID_CNTL1
+#define SMBUS_UDID_CNTL1__SMB_UDID_31_0__SHIFT                                                                0x0
+#define SMBUS_UDID_CNTL1__SMB_UDID_31_0_MASK                                                                  0xFFFFFFFFL
+//SMBUS_UDID_CNTL2
+#define SMBUS_UDID_CNTL2__PEC_SUPPORTED__SHIFT                                                                0x0
+#define SMBUS_UDID_CNTL2__UDID_VERSION__SHIFT                                                                 0x1
+#define SMBUS_UDID_CNTL2__SMBUS_VERSION__SHIFT                                                                0x4
+#define SMBUS_UDID_CNTL2__OEM__SHIFT                                                                          0x8
+#define SMBUS_UDID_CNTL2__ASF__SHIFT                                                                          0x9
+#define SMBUS_UDID_CNTL2__IPMI__SHIFT                                                                         0xa
+#define SMBUS_UDID_CNTL2__PEC_SUPPORTED_MASK                                                                  0x00000001L
+#define SMBUS_UDID_CNTL2__UDID_VERSION_MASK                                                                   0x0000000EL
+#define SMBUS_UDID_CNTL2__SMBUS_VERSION_MASK                                                                  0x000000F0L
+#define SMBUS_UDID_CNTL2__OEM_MASK                                                                            0x00000100L
+#define SMBUS_UDID_CNTL2__ASF_MASK                                                                            0x00000200L
+#define SMBUS_UDID_CNTL2__IPMI_MASK                                                                           0x00000400L
+//SMBUS_BACO_DUMMY
+#define SMBUS_BACO_DUMMY__BACO_DUMMY_DATA__SHIFT                                                              0x0
+#define SMBUS_BACO_DUMMY__BACO_DUMMY_DATA_MASK                                                                0xFFFFFFFFL
+//SMBUS_BACO_ADDR_RANGE0_LOW
+#define SMBUS_BACO_ADDR_RANGE0_LOW__BACO_ADDR_RANGE0_LOW__SHIFT                                               0x0
+#define SMBUS_BACO_ADDR_RANGE0_LOW__BACO_ADDR_RANGE0_LOW_MASK                                                 0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE0_HIGH
+#define SMBUS_BACO_ADDR_RANGE0_HIGH__BACO_ADDR_RANGE0_HIGH__SHIFT                                             0x0
+#define SMBUS_BACO_ADDR_RANGE0_HIGH__BACO_ADDR_RANGE0_HIGH_MASK                                               0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE1_LOW
+#define SMBUS_BACO_ADDR_RANGE1_LOW__BACO_ADDR_RANGE1_LOW__SHIFT                                               0x0
+#define SMBUS_BACO_ADDR_RANGE1_LOW__BACO_ADDR_RANGE1_LOW_MASK                                                 0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE1_HIGH
+#define SMBUS_BACO_ADDR_RANGE1_HIGH__BACO_ADDR_RANGE1_HIGH__SHIFT                                             0x0
+#define SMBUS_BACO_ADDR_RANGE1_HIGH__BACO_ADDR_RANGE1_HIGH_MASK                                               0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE2_LOW
+#define SMBUS_BACO_ADDR_RANGE2_LOW__BACO_ADDR_RANGE2_LOW__SHIFT                                               0x0
+#define SMBUS_BACO_ADDR_RANGE2_LOW__BACO_ADDR_RANGE2_LOW_MASK                                                 0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE2_HIGH
+#define SMBUS_BACO_ADDR_RANGE2_HIGH__BACO_ADDR_RANGE2_HIGH__SHIFT                                             0x0
+#define SMBUS_BACO_ADDR_RANGE2_HIGH__BACO_ADDR_RANGE2_HIGH_MASK                                               0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE3_LOW
+#define SMBUS_BACO_ADDR_RANGE3_LOW__BACO_ADDR_RANGE3_LOW__SHIFT                                               0x0
+#define SMBUS_BACO_ADDR_RANGE3_LOW__BACO_ADDR_RANGE3_LOW_MASK                                                 0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE3_HIGH
+#define SMBUS_BACO_ADDR_RANGE3_HIGH__BACO_ADDR_RANGE3_HIGH__SHIFT                                             0x0
+#define SMBUS_BACO_ADDR_RANGE3_HIGH__BACO_ADDR_RANGE3_HIGH_MASK                                               0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE4_LOW
+#define SMBUS_BACO_ADDR_RANGE4_LOW__BACO_ADDR_RANGE4_LOW__SHIFT                                               0x0
+#define SMBUS_BACO_ADDR_RANGE4_LOW__BACO_ADDR_RANGE4_LOW_MASK                                                 0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE4_HIGH
+#define SMBUS_BACO_ADDR_RANGE4_HIGH__BACO_ADDR_RANGE4_HIGH__SHIFT                                             0x0
+#define SMBUS_BACO_ADDR_RANGE4_HIGH__BACO_ADDR_RANGE4_HIGH_MASK                                               0x000FFFFFL
+//THM_GPIO_MACO_EN_CTRL
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL__SHIFT                                                        0x0
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PD__SHIFT                                                              0x1
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PU__SHIFT                                                              0x2
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN__SHIFT                                                          0x3
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S0__SHIFT                                                              0x4
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S1__SHIFT                                                              0x5
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN__SHIFT                                                            0x6
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0__SHIFT                                                          0x7
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1__SHIFT                                                          0x8
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE__SHIFT                                                     0x10
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE__SHIFT                                                              0x11
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE__SHIFT                                                      0x12
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A__SHIFT                                                               0x13
+#define THM_GPIO_MACO_EN_CTRL__Y__SHIFT                                                                       0x1f
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL_MASK                                                          0x00000001L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PD_MASK                                                                0x00000002L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PU_MASK                                                                0x00000004L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN_MASK                                                            0x00000008L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S0_MASK                                                                0x00000010L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S1_MASK                                                                0x00000020L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN_MASK                                                              0x00000040L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0_MASK                                                            0x00000080L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1_MASK                                                            0x00000100L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE_MASK                                                       0x00010000L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_MASK                                                                0x00020000L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE_MASK                                                        0x00040000L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_MASK                                                                 0x00080000L
+#define THM_GPIO_MACO_EN_CTRL__Y_MASK                                                                         0x80000000L
+//THM_BACO_TIMING2
+#define THM_BACO_TIMING2__BACO_AEB_ISO_EXIT_CNT__SHIFT                                                        0x0
+#define THM_BACO_TIMING2__BACO_ANA_ISO_EXIT_CNT__SHIFT                                                        0x8
+#define THM_BACO_TIMING2__BACO_EXIT_CNT__SHIFT                                                                0x10
+#define THM_BACO_TIMING2__BACO_AEB_ISO_EXIT_CNT_MASK                                                          0x000000FFL
+#define THM_BACO_TIMING2__BACO_ANA_ISO_EXIT_CNT_MASK                                                          0x0000FF00L
+#define THM_BACO_TIMING2__BACO_EXIT_CNT_MASK                                                                  0x00FF0000L
+//THM_BACO_TIMING
+#define THM_BACO_TIMING__BACO_RESET_DELAY__SHIFT                                                              0x0
+#define THM_BACO_TIMING__BACO_RESET_DELAY_MASK                                                                0x0000FFFFL
+//THM_TMON0_REMOTE_START
+#define THM_TMON0_REMOTE_START__DATA__SHIFT                                                                   0x0
+#define THM_TMON0_REMOTE_START__DATA_MASK                                                                     0xFFFFFFFFL
+//THM_TMON0_REMOTE_END
+#define THM_TMON0_REMOTE_END__DATA__SHIFT                                                                     0x0
+#define THM_TMON0_REMOTE_END__DATA_MASK                                                                       0xFFFFFFFFL
+//THM_TMON1_REMOTE_START
+#define THM_TMON1_REMOTE_START__DATA__SHIFT                                                                   0x0
+#define THM_TMON1_REMOTE_START__DATA_MASK                                                                     0xFFFFFFFFL
+//THM_TMON1_REMOTE_END
+#define THM_TMON1_REMOTE_END__DATA__SHIFT                                                                     0x0
+#define THM_TMON1_REMOTE_END__DATA_MASK                                                                       0xFFFFFFFFL
+//THM_TMON2_REMOTE_START
+#define THM_TMON2_REMOTE_START__DATA__SHIFT                                                                   0x0
+#define THM_TMON2_REMOTE_START__DATA_MASK                                                                     0xFFFFFFFFL
+//THM_TMON2_REMOTE_END
+#define THM_TMON2_REMOTE_END__DATA__SHIFT                                                                     0x0
+#define THM_TMON2_REMOTE_END__DATA_MASK                                                                       0xFFFFFFFFL
+//THM_TMON3_REMOTE_START
+#define THM_TMON3_REMOTE_START__DATA__SHIFT                                                                   0x0
+#define THM_TMON3_REMOTE_START__DATA_MASK                                                                     0xFFFFFFFFL
+//THM_TMON3_REMOTE_END
+#define THM_TMON3_REMOTE_END__DATA__SHIFT                                                                     0x0
+#define THM_TMON3_REMOTE_END__DATA_MASK                                                                       0xFFFFFFFFL
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h
deleted file mode 100644
index 0cbae8b..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * Copyright (C) 2017  Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _thm_9_0_DEFAULT_HEADER
-#define _thm_9_0_DEFAULT_HEADER
-
-
-// addressBlock: thm_thm_SmuThmDec
-#define mmTHM_TCON_CUR_TMP_DEFAULT                                               0x00000000
-#define mmTHM_TCON_HTC_DEFAULT                                                   0x00004000
-#define mmTHM_TCON_THERM_TRIP_DEFAULT                                            0x00000001
-#define mmTHM_GPIO_PROCHOT_CTRL_DEFAULT                                          0x000000f9
-#define mmTHM_GPIO_THERMTRIP_CTRL_DEFAULT                                        0x001000f9
-#define mmTHM_GPIO_PWM_CTRL_DEFAULT                                              0x000000f9
-#define mmTHM_GPIO_TACHIN_CTRL_DEFAULT                                           0x000000f9
-#define mmTHM_GPIO_PUMPOUT_CTRL_DEFAULT                                          0x000000f9
-#define mmTHM_GPIO_PUMPIN_CTRL_DEFAULT                                           0x000000f9
-#define mmTHM_THERMAL_INT_ENA_DEFAULT                                            0x00000000
-#define mmTHM_THERMAL_INT_CTRL_DEFAULT                                           0x0fff0078
-#define mmTHM_THERMAL_INT_STATUS_DEFAULT                                         0x00000000
-#define mmTHM_TMON0_RDIL0_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIL1_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIL2_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIL3_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIL4_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIL5_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIL6_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIL7_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIL8_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIL9_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIL10_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON0_RDIL11_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON0_RDIL12_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON0_RDIL13_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON0_RDIL14_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON0_RDIL15_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON0_RDIR0_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIR1_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIR2_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIR3_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIR4_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIR5_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIR6_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIR7_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIR8_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIR9_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON0_RDIR10_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON0_RDIR11_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON0_RDIR12_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON0_RDIR13_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON0_RDIR14_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON0_RDIR15_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON0_INT_DATA_DEFAULT                                             0x00000000
-#define mmTHM_TMON0_DEBUG_DEFAULT                                                0x00000000
-#define mmTHM_TMON1_RDIL0_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIL1_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIL2_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIL3_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIL4_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIL5_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIL6_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIL7_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIL8_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIL9_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIL10_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON1_RDIL11_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON1_RDIL12_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON1_RDIL13_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON1_RDIL14_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON1_RDIL15_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON1_RDIR0_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIR1_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIR2_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIR3_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIR4_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIR5_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIR6_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIR7_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIR8_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIR9_DATA_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_RDIR10_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON1_RDIR11_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON1_RDIR12_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON1_RDIR13_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON1_RDIR14_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON1_RDIR15_DATA_DEFAULT                                          0x00000000
-#define mmTHM_TMON1_INT_DATA_DEFAULT                                             0x00000000
-#define mmTHM_TMON1_DEBUG_DEFAULT                                                0x00000000
-#define mmTHM_DIE1_TEMP_DEFAULT                                                  0x00000000
-#define mmTHM_DIE2_TEMP_DEFAULT                                                  0x00000000
-#define mmTHM_DIE3_TEMP_DEFAULT                                                  0x00000000
-#define mmCG_MULT_THERMAL_CTRL_DEFAULT                                           0x08400001
-#define mmCG_MULT_THERMAL_STATUS_DEFAULT                                         0x00000000
-#define mmTHM_TMON0_COEFF_DEFAULT                                                0x00024068
-#define mmTHM_TMON1_COEFF_DEFAULT                                                0x00024068
-#define mmCG_FDO_CTRL0_DEFAULT                                                   0x0000642c
-#define mmCG_FDO_CTRL1_DEFAULT                                                   0x001e1f7d
-#define mmCG_FDO_CTRL2_DEFAULT                                                   0x02bf0228
-#define mmCG_TACH_CTRL_DEFAULT                                                   0x00008002
-#define mmCG_TACH_STATUS_DEFAULT                                                 0x00000000
-#define mmCG_THERMAL_STATUS_DEFAULT                                              0x00000000
-#define mmCG_PUMP_CTRL0_DEFAULT                                                  0x0000642c
-#define mmCG_PUMP_CTRL1_DEFAULT                                                  0x001e1f7d
-#define mmCG_PUMP_CTRL2_DEFAULT                                                  0x02bf0228
-#define mmCG_PUMP_TACH_CTRL_DEFAULT                                              0x00008002
-#define mmCG_PUMP_TACH_STATUS_DEFAULT                                            0x00000000
-#define mmCG_PUMP_STATUS_DEFAULT                                                 0x00000000
-#define mmTHM_TCON_LOCAL0_DEFAULT                                                0x00000000
-#define mmTHM_TCON_LOCAL1_DEFAULT                                                0x00000000
-#define mmTHM_TCON_LOCAL2_DEFAULT                                                0x00000060
-#define mmTHM_TCON_LOCAL3_DEFAULT                                                0x00000000
-#define mmTHM_TCON_LOCAL4_DEFAULT                                                0x00000000
-#define mmTHM_TCON_LOCAL5_DEFAULT                                                0x00000000
-#define mmTHM_TCON_LOCAL6_DEFAULT                                                0x00000000
-#define mmTHM_TCON_LOCAL7_DEFAULT                                                0x00000000
-#define mmTHM_TCON_LOCAL8_DEFAULT                                                0x00000000
-#define mmTHM_TCON_LOCAL9_DEFAULT                                                0x00000000
-#define mmTHM_TCON_LOCAL10_DEFAULT                                               0x00000000
-#define mmTHM_TCON_LOCAL11_DEFAULT                                               0x00000000
-#define mmTHM_TCON_LOCAL12_DEFAULT                                               0x00000000
-#define mmTHM_TCON_LOCAL13_DEFAULT                                               0x00000000
-#define mmTHM_BACO_CNTL_DEFAULT                                                  0x00000004
-#define mmTHM_BACO_TIMING0_DEFAULT                                               0x80a06050
-#define mmTHM_BACO_TIMING1_DEFAULT                                               0x1020f070
-#define mmXTAL_CNTL_DEFAULT                                                      0x00006010
-#define mmSBTSI_REMOTE_TEMP_DEFAULT                                              0x00000000
-#define mmSBRMI_CONTROL_DEFAULT                                                  0x00000000
-#define mmSBRMI_COMMAND_DEFAULT                                                  0x00000000
-#define mmSBRMI_WRITE_DATA0_DEFAULT                                              0x00000000
-#define mmSBRMI_WRITE_DATA1_DEFAULT                                              0x00000000
-#define mmSBRMI_WRITE_DATA2_DEFAULT                                              0x00000000
-#define mmSBRMI_READ_DATA0_DEFAULT                                               0x00000000
-#define mmSBRMI_READ_DATA1_DEFAULT                                               0x00000000
-#define mmSBRMI_CORE_EN_NUMBER_DEFAULT                                           0x00000010
-#define mmSBRMI_CORE_EN_STATUS0_DEFAULT                                          0x00000000
-#define mmSBRMI_CORE_EN_STATUS1_DEFAULT                                          0x00000000
-#define mmSBRMI_APIC_STATUS0_DEFAULT                                             0x00000000
-#define mmSBRMI_APIC_STATUS1_DEFAULT                                             0x00000000
-#define mmSBRMI_MCE_STATUS0_DEFAULT                                              0x00000000
-#define mmSBRMI_MCE_STATUS1_DEFAULT                                              0x00000000
-#define mmSMBUS_CNTL0_DEFAULT                                                    0x00030082
-#define mmSMBUS_CNTL1_DEFAULT                                                    0x0000063f
-#define mmSMBUS_BLKWR_CMD_CTRL0_DEFAULT                                          0x12110201
-#define mmSMBUS_BLKWR_CMD_CTRL1_DEFAULT                                          0x0003005a
-#define mmSMBUS_BLKRD_CMD_CTRL0_DEFAULT                                          0x00001303
-#define mmSMBUS_BLKRD_CMD_CTRL1_DEFAULT                                          0x00000000
-#define mmSMBUS_TIMING_CNTL0_DEFAULT                                             0x028a4f5c
-#define mmSMBUS_TIMING_CNTL1_DEFAULT                                             0x08036927
-#define mmSMBUS_TIMING_CNTL2_DEFAULT                                             0x0021e548
-#define mmSMBUS_TRIGGER_CNTL_DEFAULT                                             0x00000000
-#define mmSMBUS_UDID_CNTL0_DEFAULT                                               0x7fffffff
-#define mmSMBUS_UDID_CNTL1_DEFAULT                                               0x00000000
-#define mmSMBUS_UDID_CNTL2_DEFAULT                                               0x00000043
-#define mmSMBUS_BACO_DUMMY_DEFAULT                                               0x00000000
-#define mmSMBUS_BACO_ADDR_RANGE0_LOW_DEFAULT                                     0x00000000
-#define mmSMBUS_BACO_ADDR_RANGE0_HIGH_DEFAULT                                    0x00000000
-#define mmSMBUS_BACO_ADDR_RANGE1_LOW_DEFAULT                                     0x00000000
-#define mmSMBUS_BACO_ADDR_RANGE1_HIGH_DEFAULT                                    0x00000000
-#define mmSMBUS_BACO_ADDR_RANGE2_LOW_DEFAULT                                     0x00000000
-#define mmSMBUS_BACO_ADDR_RANGE2_HIGH_DEFAULT                                    0x00000000
-#define mmSMBUS_BACO_ADDR_RANGE3_LOW_DEFAULT                                     0x00000000
-#define mmSMBUS_BACO_ADDR_RANGE3_HIGH_DEFAULT                                    0x00000000
-#define mmSMBUS_BACO_ADDR_RANGE4_LOW_DEFAULT                                     0x00000000
-#define mmSMBUS_BACO_ADDR_RANGE4_HIGH_DEFAULT                                    0x00000000
-#define mmTHM_GPIO_MACO_EN_CTRL_DEFAULT                                          0x000000f9
-#define mmTHM_BACO_TIMING2_DEFAULT                                               0x00903040
-#define mmTHM_BACO_TIMING_DEFAULT                                                0x00000a8c
-#define mmTHM_TMON0_REMOTE_START_DEFAULT                                         0x00000000
-#define mmTHM_TMON0_REMOTE_END_DEFAULT                                           0x00000000
-#define mmTHM_TMON1_REMOTE_START_DEFAULT                                         0x00000000
-#define mmTHM_TMON1_REMOTE_END_DEFAULT                                           0x00000000
-#define mmTHM_TMON2_REMOTE_START_DEFAULT                                         0x00000000
-#define mmTHM_TMON2_REMOTE_END_DEFAULT                                           0x00000000
-#define mmTHM_TMON3_REMOTE_START_DEFAULT                                         0x00000000
-#define mmTHM_TMON3_REMOTE_END_DEFAULT                                           0x00000000
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h
deleted file mode 100644
index 3053fd3..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * Copyright (C) 2017  Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _thm_9_0_OFFSET_HEADER
-#define _thm_9_0_OFFSET_HEADER
-
-
-
-// addressBlock: thm_thm_SmuThmDec
-// base address: 0x59800
-#define mmTHM_TCON_CUR_TMP                                                                             0x0000
-#define mmTHM_TCON_CUR_TMP_BASE_IDX                                                                    0
-#define mmTHM_TCON_HTC                                                                                 0x0001
-#define mmTHM_TCON_HTC_BASE_IDX                                                                        0
-#define mmTHM_TCON_THERM_TRIP                                                                          0x0002
-#define mmTHM_TCON_THERM_TRIP_BASE_IDX                                                                 0
-#define mmTHM_GPIO_PROCHOT_CTRL                                                                        0x0004
-#define mmTHM_GPIO_PROCHOT_CTRL_BASE_IDX                                                               0
-#define mmTHM_GPIO_THERMTRIP_CTRL                                                                      0x0005
-#define mmTHM_GPIO_THERMTRIP_CTRL_BASE_IDX                                                             0
-#define mmTHM_GPIO_PWM_CTRL                                                                            0x0006
-#define mmTHM_GPIO_PWM_CTRL_BASE_IDX                                                                   0
-#define mmTHM_GPIO_TACHIN_CTRL                                                                         0x0007
-#define mmTHM_GPIO_TACHIN_CTRL_BASE_IDX                                                                0
-#define mmTHM_GPIO_PUMPOUT_CTRL                                                                        0x0008
-#define mmTHM_GPIO_PUMPOUT_CTRL_BASE_IDX                                                               0
-#define mmTHM_GPIO_PUMPIN_CTRL                                                                         0x0009
-#define mmTHM_GPIO_PUMPIN_CTRL_BASE_IDX                                                                0
-#define mmTHM_THERMAL_INT_ENA                                                                          0x000a
-#define mmTHM_THERMAL_INT_ENA_BASE_IDX                                                                 0
-#define mmTHM_THERMAL_INT_CTRL                                                                         0x000b
-#define mmTHM_THERMAL_INT_CTRL_BASE_IDX                                                                0
-#define mmTHM_THERMAL_INT_STATUS                                                                       0x000c
-#define mmTHM_THERMAL_INT_STATUS_BASE_IDX                                                              0
-#define mmTHM_TMON0_RDIL0_DATA                                                                         0x000d
-#define mmTHM_TMON0_RDIL0_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIL1_DATA                                                                         0x000e
-#define mmTHM_TMON0_RDIL1_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIL2_DATA                                                                         0x000f
-#define mmTHM_TMON0_RDIL2_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIL3_DATA                                                                         0x0010
-#define mmTHM_TMON0_RDIL3_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIL4_DATA                                                                         0x0011
-#define mmTHM_TMON0_RDIL4_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIL5_DATA                                                                         0x0012
-#define mmTHM_TMON0_RDIL5_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIL6_DATA                                                                         0x0013
-#define mmTHM_TMON0_RDIL6_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIL7_DATA                                                                         0x0014
-#define mmTHM_TMON0_RDIL7_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIL8_DATA                                                                         0x0015
-#define mmTHM_TMON0_RDIL8_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIL9_DATA                                                                         0x0016
-#define mmTHM_TMON0_RDIL9_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIL10_DATA                                                                        0x0017
-#define mmTHM_TMON0_RDIL10_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON0_RDIL11_DATA                                                                        0x0018
-#define mmTHM_TMON0_RDIL11_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON0_RDIL12_DATA                                                                        0x0019
-#define mmTHM_TMON0_RDIL12_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON0_RDIL13_DATA                                                                        0x001a
-#define mmTHM_TMON0_RDIL13_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON0_RDIL14_DATA                                                                        0x001b
-#define mmTHM_TMON0_RDIL14_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON0_RDIL15_DATA                                                                        0x001c
-#define mmTHM_TMON0_RDIL15_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON0_RDIR0_DATA                                                                         0x001d
-#define mmTHM_TMON0_RDIR0_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIR1_DATA                                                                         0x001e
-#define mmTHM_TMON0_RDIR1_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIR2_DATA                                                                         0x001f
-#define mmTHM_TMON0_RDIR2_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIR3_DATA                                                                         0x0020
-#define mmTHM_TMON0_RDIR3_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIR4_DATA                                                                         0x0021
-#define mmTHM_TMON0_RDIR4_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIR5_DATA                                                                         0x0022
-#define mmTHM_TMON0_RDIR5_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIR6_DATA                                                                         0x0023
-#define mmTHM_TMON0_RDIR6_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIR7_DATA                                                                         0x0024
-#define mmTHM_TMON0_RDIR7_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIR8_DATA                                                                         0x0025
-#define mmTHM_TMON0_RDIR8_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIR9_DATA                                                                         0x0026
-#define mmTHM_TMON0_RDIR9_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON0_RDIR10_DATA                                                                        0x0027
-#define mmTHM_TMON0_RDIR10_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON0_RDIR11_DATA                                                                        0x0028
-#define mmTHM_TMON0_RDIR11_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON0_RDIR12_DATA                                                                        0x0029
-#define mmTHM_TMON0_RDIR12_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON0_RDIR13_DATA                                                                        0x002a
-#define mmTHM_TMON0_RDIR13_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON0_RDIR14_DATA                                                                        0x002b
-#define mmTHM_TMON0_RDIR14_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON0_RDIR15_DATA                                                                        0x002c
-#define mmTHM_TMON0_RDIR15_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON0_INT_DATA                                                                           0x002d
-#define mmTHM_TMON0_INT_DATA_BASE_IDX                                                                  0
-#define mmTHM_TMON0_DEBUG                                                                              0x0030
-#define mmTHM_TMON0_DEBUG_BASE_IDX                                                                     0
-#define mmTHM_TMON1_RDIL0_DATA                                                                         0x0031
-#define mmTHM_TMON1_RDIL0_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIL1_DATA                                                                         0x0032
-#define mmTHM_TMON1_RDIL1_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIL2_DATA                                                                         0x0033
-#define mmTHM_TMON1_RDIL2_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIL3_DATA                                                                         0x0034
-#define mmTHM_TMON1_RDIL3_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIL4_DATA                                                                         0x0035
-#define mmTHM_TMON1_RDIL4_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIL5_DATA                                                                         0x0036
-#define mmTHM_TMON1_RDIL5_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIL6_DATA                                                                         0x0037
-#define mmTHM_TMON1_RDIL6_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIL7_DATA                                                                         0x0038
-#define mmTHM_TMON1_RDIL7_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIL8_DATA                                                                         0x0039
-#define mmTHM_TMON1_RDIL8_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIL9_DATA                                                                         0x003a
-#define mmTHM_TMON1_RDIL9_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIL10_DATA                                                                        0x003b
-#define mmTHM_TMON1_RDIL10_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON1_RDIL11_DATA                                                                        0x003c
-#define mmTHM_TMON1_RDIL11_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON1_RDIL12_DATA                                                                        0x003d
-#define mmTHM_TMON1_RDIL12_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON1_RDIL13_DATA                                                                        0x003e
-#define mmTHM_TMON1_RDIL13_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON1_RDIL14_DATA                                                                        0x003f
-#define mmTHM_TMON1_RDIL14_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON1_RDIL15_DATA                                                                        0x0040
-#define mmTHM_TMON1_RDIL15_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON1_RDIR0_DATA                                                                         0x0041
-#define mmTHM_TMON1_RDIR0_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIR1_DATA                                                                         0x0042
-#define mmTHM_TMON1_RDIR1_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIR2_DATA                                                                         0x0043
-#define mmTHM_TMON1_RDIR2_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIR3_DATA                                                                         0x0044
-#define mmTHM_TMON1_RDIR3_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIR4_DATA                                                                         0x0045
-#define mmTHM_TMON1_RDIR4_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIR5_DATA                                                                         0x0046
-#define mmTHM_TMON1_RDIR5_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIR6_DATA                                                                         0x0047
-#define mmTHM_TMON1_RDIR6_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIR7_DATA                                                                         0x0048
-#define mmTHM_TMON1_RDIR7_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIR8_DATA                                                                         0x0049
-#define mmTHM_TMON1_RDIR8_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIR9_DATA                                                                         0x004a
-#define mmTHM_TMON1_RDIR9_DATA_BASE_IDX                                                                0
-#define mmTHM_TMON1_RDIR10_DATA                                                                        0x004b
-#define mmTHM_TMON1_RDIR10_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON1_RDIR11_DATA                                                                        0x004c
-#define mmTHM_TMON1_RDIR11_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON1_RDIR12_DATA                                                                        0x004d
-#define mmTHM_TMON1_RDIR12_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON1_RDIR13_DATA                                                                        0x004e
-#define mmTHM_TMON1_RDIR13_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON1_RDIR14_DATA                                                                        0x004f
-#define mmTHM_TMON1_RDIR14_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON1_RDIR15_DATA                                                                        0x0050
-#define mmTHM_TMON1_RDIR15_DATA_BASE_IDX                                                               0
-#define mmTHM_TMON1_INT_DATA                                                                           0x0051
-#define mmTHM_TMON1_INT_DATA_BASE_IDX                                                                  0
-#define mmTHM_TMON1_DEBUG                                                                              0x0054
-#define mmTHM_TMON1_DEBUG_BASE_IDX                                                                     0
-#define mmTHM_DIE1_TEMP                                                                                0x0055
-#define mmTHM_DIE1_TEMP_BASE_IDX                                                                       0
-#define mmTHM_DIE2_TEMP                                                                                0x0056
-#define mmTHM_DIE2_TEMP_BASE_IDX                                                                       0
-#define mmTHM_DIE3_TEMP                                                                                0x0057
-#define mmTHM_DIE3_TEMP_BASE_IDX                                                                       0
-#define mmCG_MULT_THERMAL_CTRL                                                                         0x0059
-#define mmCG_MULT_THERMAL_CTRL_BASE_IDX                                                                0
-#define mmCG_MULT_THERMAL_STATUS                                                                       0x005a
-#define mmCG_MULT_THERMAL_STATUS_BASE_IDX                                                              0
-#define mmTHM_TMON0_COEFF                                                                              0x005e
-#define mmTHM_TMON0_COEFF_BASE_IDX                                                                     0
-#define mmTHM_TMON1_COEFF                                                                              0x005f
-#define mmTHM_TMON1_COEFF_BASE_IDX                                                                     0
-#define mmCG_FDO_CTRL0                                                                                 0x0062
-#define mmCG_FDO_CTRL0_BASE_IDX                                                                        0
-#define mmCG_FDO_CTRL1                                                                                 0x0063
-#define mmCG_FDO_CTRL1_BASE_IDX                                                                        0
-#define mmCG_FDO_CTRL2                                                                                 0x0064
-#define mmCG_FDO_CTRL2_BASE_IDX                                                                        0
-#define mmCG_TACH_CTRL                                                                                 0x0065
-#define mmCG_TACH_CTRL_BASE_IDX                                                                        0
-#define mmCG_TACH_STATUS                                                                               0x0066
-#define mmCG_TACH_STATUS_BASE_IDX                                                                      0
-#define mmCG_THERMAL_STATUS                                                                            0x0067
-#define mmCG_THERMAL_STATUS_BASE_IDX                                                                   0
-#define mmCG_PUMP_CTRL0                                                                                0x0068
-#define mmCG_PUMP_CTRL0_BASE_IDX                                                                       0
-#define mmCG_PUMP_CTRL1                                                                                0x0069
-#define mmCG_PUMP_CTRL1_BASE_IDX                                                                       0
-#define mmCG_PUMP_CTRL2                                                                                0x006a
-#define mmCG_PUMP_CTRL2_BASE_IDX                                                                       0
-#define mmCG_PUMP_TACH_CTRL                                                                            0x006b
-#define mmCG_PUMP_TACH_CTRL_BASE_IDX                                                                   0
-#define mmCG_PUMP_TACH_STATUS                                                                          0x006c
-#define mmCG_PUMP_TACH_STATUS_BASE_IDX                                                                 0
-#define mmCG_PUMP_STATUS                                                                               0x006d
-#define mmCG_PUMP_STATUS_BASE_IDX                                                                      0
-#define mmTHM_TCON_LOCAL0                                                                              0x006e
-#define mmTHM_TCON_LOCAL0_BASE_IDX                                                                     0
-#define mmTHM_TCON_LOCAL1                                                                              0x006f
-#define mmTHM_TCON_LOCAL1_BASE_IDX                                                                     0
-#define mmTHM_TCON_LOCAL2                                                                              0x0070
-#define mmTHM_TCON_LOCAL2_BASE_IDX                                                                     0
-#define mmTHM_TCON_LOCAL3                                                                              0x0071
-#define mmTHM_TCON_LOCAL3_BASE_IDX                                                                     0
-#define mmTHM_TCON_LOCAL4                                                                              0x0072
-#define mmTHM_TCON_LOCAL4_BASE_IDX                                                                     0
-#define mmTHM_TCON_LOCAL5                                                                              0x0073
-#define mmTHM_TCON_LOCAL5_BASE_IDX                                                                     0
-#define mmTHM_TCON_LOCAL6                                                                              0x0074
-#define mmTHM_TCON_LOCAL6_BASE_IDX                                                                     0
-#define mmTHM_TCON_LOCAL7                                                                              0x0075
-#define mmTHM_TCON_LOCAL7_BASE_IDX                                                                     0
-#define mmTHM_TCON_LOCAL8                                                                              0x0076
-#define mmTHM_TCON_LOCAL8_BASE_IDX                                                                     0
-#define mmTHM_TCON_LOCAL9                                                                              0x0077
-#define mmTHM_TCON_LOCAL9_BASE_IDX                                                                     0
-#define mmTHM_TCON_LOCAL10                                                                             0x0078
-#define mmTHM_TCON_LOCAL10_BASE_IDX                                                                    0
-#define mmTHM_TCON_LOCAL11                                                                             0x0079
-#define mmTHM_TCON_LOCAL11_BASE_IDX                                                                    0
-#define mmTHM_TCON_LOCAL12                                                                             0x007a
-#define mmTHM_TCON_LOCAL12_BASE_IDX                                                                    0
-#define mmTHM_TCON_LOCAL13                                                                             0x007b
-#define mmTHM_TCON_LOCAL13_BASE_IDX                                                                    0
-#define mmTHM_BACO_CNTL                                                                                0x007c
-#define mmTHM_BACO_CNTL_BASE_IDX                                                                       0
-#define mmTHM_BACO_TIMING0                                                                             0x007d
-#define mmTHM_BACO_TIMING0_BASE_IDX                                                                    0
-#define mmTHM_BACO_TIMING1                                                                             0x007e
-#define mmTHM_BACO_TIMING1_BASE_IDX                                                                    0
-#define mmXTAL_CNTL                                                                                    0x007f
-#define mmXTAL_CNTL_BASE_IDX                                                                           0
-#define mmSBTSI_REMOTE_TEMP                                                                            0x008a
-#define mmSBTSI_REMOTE_TEMP_BASE_IDX                                                                   0
-#define mmSBRMI_CONTROL                                                                                0x008b
-#define mmSBRMI_CONTROL_BASE_IDX                                                                       0
-#define mmSBRMI_COMMAND                                                                                0x008c
-#define mmSBRMI_COMMAND_BASE_IDX                                                                       0
-#define mmSBRMI_WRITE_DATA0                                                                            0x008d
-#define mmSBRMI_WRITE_DATA0_BASE_IDX                                                                   0
-#define mmSBRMI_WRITE_DATA1                                                                            0x008e
-#define mmSBRMI_WRITE_DATA1_BASE_IDX                                                                   0
-#define mmSBRMI_WRITE_DATA2                                                                            0x008f
-#define mmSBRMI_WRITE_DATA2_BASE_IDX                                                                   0
-#define mmSBRMI_READ_DATA0                                                                             0x0090
-#define mmSBRMI_READ_DATA0_BASE_IDX                                                                    0
-#define mmSBRMI_READ_DATA1                                                                             0x0091
-#define mmSBRMI_READ_DATA1_BASE_IDX                                                                    0
-#define mmSBRMI_CORE_EN_NUMBER                                                                         0x0092
-#define mmSBRMI_CORE_EN_NUMBER_BASE_IDX                                                                0
-#define mmSBRMI_CORE_EN_STATUS0                                                                        0x0093
-#define mmSBRMI_CORE_EN_STATUS0_BASE_IDX                                                               0
-#define mmSBRMI_CORE_EN_STATUS1                                                                        0x0094
-#define mmSBRMI_CORE_EN_STATUS1_BASE_IDX                                                               0
-#define mmSBRMI_APIC_STATUS0                                                                           0x0095
-#define mmSBRMI_APIC_STATUS0_BASE_IDX                                                                  0
-#define mmSBRMI_APIC_STATUS1                                                                           0x0096
-#define mmSBRMI_APIC_STATUS1_BASE_IDX                                                                  0
-#define mmSBRMI_MCE_STATUS0                                                                            0x0097
-#define mmSBRMI_MCE_STATUS0_BASE_IDX                                                                   0
-#define mmSBRMI_MCE_STATUS1                                                                            0x0098
-#define mmSBRMI_MCE_STATUS1_BASE_IDX                                                                   0
-#define mmSMBUS_CNTL0                                                                                  0x0099
-#define mmSMBUS_CNTL0_BASE_IDX                                                                         0
-#define mmSMBUS_CNTL1                                                                                  0x009a
-#define mmSMBUS_CNTL1_BASE_IDX                                                                         0
-#define mmSMBUS_BLKWR_CMD_CTRL0                                                                        0x009b
-#define mmSMBUS_BLKWR_CMD_CTRL0_BASE_IDX                                                               0
-#define mmSMBUS_BLKWR_CMD_CTRL1                                                                        0x009c
-#define mmSMBUS_BLKWR_CMD_CTRL1_BASE_IDX                                                               0
-#define mmSMBUS_BLKRD_CMD_CTRL0                                                                        0x009d
-#define mmSMBUS_BLKRD_CMD_CTRL0_BASE_IDX                                                               0
-#define mmSMBUS_BLKRD_CMD_CTRL1                                                                        0x009e
-#define mmSMBUS_BLKRD_CMD_CTRL1_BASE_IDX                                                               0
-#define mmSMBUS_TIMING_CNTL0                                                                           0x009f
-#define mmSMBUS_TIMING_CNTL0_BASE_IDX                                                                  0
-#define mmSMBUS_TIMING_CNTL1                                                                           0x00a0
-#define mmSMBUS_TIMING_CNTL1_BASE_IDX                                                                  0
-#define mmSMBUS_TIMING_CNTL2                                                                           0x00a1
-#define mmSMBUS_TIMING_CNTL2_BASE_IDX                                                                  0
-#define mmSMBUS_TRIGGER_CNTL                                                                           0x00a2
-#define mmSMBUS_TRIGGER_CNTL_BASE_IDX                                                                  0
-#define mmSMBUS_UDID_CNTL0                                                                             0x00a3
-#define mmSMBUS_UDID_CNTL0_BASE_IDX                                                                    0
-#define mmSMBUS_UDID_CNTL1                                                                             0x00a4
-#define mmSMBUS_UDID_CNTL1_BASE_IDX                                                                    0
-#define mmSMBUS_UDID_CNTL2                                                                             0x00a5
-#define mmSMBUS_UDID_CNTL2_BASE_IDX                                                                    0
-#define mmSMBUS_BACO_DUMMY                                                                             0x00a8
-#define mmSMBUS_BACO_DUMMY_BASE_IDX                                                                    0
-#define mmSMBUS_BACO_ADDR_RANGE0_LOW                                                                   0x00a9
-#define mmSMBUS_BACO_ADDR_RANGE0_LOW_BASE_IDX                                                          0
-#define mmSMBUS_BACO_ADDR_RANGE0_HIGH                                                                  0x00aa
-#define mmSMBUS_BACO_ADDR_RANGE0_HIGH_BASE_IDX                                                         0
-#define mmSMBUS_BACO_ADDR_RANGE1_LOW                                                                   0x00ab
-#define mmSMBUS_BACO_ADDR_RANGE1_LOW_BASE_IDX                                                          0
-#define mmSMBUS_BACO_ADDR_RANGE1_HIGH                                                                  0x00ac
-#define mmSMBUS_BACO_ADDR_RANGE1_HIGH_BASE_IDX                                                         0
-#define mmSMBUS_BACO_ADDR_RANGE2_LOW                                                                   0x00ad
-#define mmSMBUS_BACO_ADDR_RANGE2_LOW_BASE_IDX                                                          0
-#define mmSMBUS_BACO_ADDR_RANGE2_HIGH                                                                  0x00ae
-#define mmSMBUS_BACO_ADDR_RANGE2_HIGH_BASE_IDX                                                         0
-#define mmSMBUS_BACO_ADDR_RANGE3_LOW                                                                   0x00af
-#define mmSMBUS_BACO_ADDR_RANGE3_LOW_BASE_IDX                                                          0
-#define mmSMBUS_BACO_ADDR_RANGE3_HIGH                                                                  0x00b0
-#define mmSMBUS_BACO_ADDR_RANGE3_HIGH_BASE_IDX                                                         0
-#define mmSMBUS_BACO_ADDR_RANGE4_LOW                                                                   0x00b1
-#define mmSMBUS_BACO_ADDR_RANGE4_LOW_BASE_IDX                                                          0
-#define mmSMBUS_BACO_ADDR_RANGE4_HIGH                                                                  0x00b2
-#define mmSMBUS_BACO_ADDR_RANGE4_HIGH_BASE_IDX                                                         0
-#define mmTHM_GPIO_MACO_EN_CTRL                                                                        0x00bd
-#define mmTHM_GPIO_MACO_EN_CTRL_BASE_IDX                                                               0
-#define mmTHM_BACO_TIMING2                                                                             0x00bf
-#define mmTHM_BACO_TIMING2_BASE_IDX                                                                    0
-#define mmTHM_BACO_TIMING                                                                              0x00c0
-#define mmTHM_BACO_TIMING_BASE_IDX                                                                     0
-#define mmTHM_TMON0_REMOTE_START                                                                       0x0100
-#define mmTHM_TMON0_REMOTE_START_BASE_IDX                                                              0
-#define mmTHM_TMON0_REMOTE_END                                                                         0x013f
-#define mmTHM_TMON0_REMOTE_END_BASE_IDX                                                                0
-#define mmTHM_TMON1_REMOTE_START                                                                       0x0140
-#define mmTHM_TMON1_REMOTE_START_BASE_IDX                                                              0
-#define mmTHM_TMON1_REMOTE_END                                                                         0x017f
-#define mmTHM_TMON1_REMOTE_END_BASE_IDX                                                                0
-#define mmTHM_TMON2_REMOTE_START                                                                       0x0180
-#define mmTHM_TMON2_REMOTE_START_BASE_IDX                                                              0
-#define mmTHM_TMON2_REMOTE_END                                                                         0x01bf
-#define mmTHM_TMON2_REMOTE_END_BASE_IDX                                                                0
-#define mmTHM_TMON3_REMOTE_START                                                                       0x01c0
-#define mmTHM_TMON3_REMOTE_START_BASE_IDX                                                              0
-#define mmTHM_TMON3_REMOTE_END                                                                         0x01ff
-#define mmTHM_TMON3_REMOTE_END_BASE_IDX                                                                0
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h
deleted file mode 100644
index f0306c5..0000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h
+++ /dev/null
@@ -1,1314 +0,0 @@
-/*
- * Copyright (C) 2017  Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _thm_9_0_SH_MASK_HEADER
-#define _thm_9_0_SH_MASK_HEADER
-
-
-// addressBlock: thm_thm_SmuThmDec
-//THM_TCON_CUR_TMP
-#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT                                                             0x0
-#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT                                                              0x5
-#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT                                                               0x7
-#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT                                                             0x8
-#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT                                                              0x10
-#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT                                                         0x12
-#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT                                                           0x13
-#define THM_TCON_CUR_TMP__MCM_EN__SHIFT                                                                       0x14
-#define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT                                                                     0x15
-#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK                                                               0x0000001FL
-#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK                                                                0x00000060L
-#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK                                                                 0x00000080L
-#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK                                                               0x00001F00L
-#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK                                                                0x00030000L
-#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK                                                           0x00040000L
-#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK                                                             0x00080000L
-#define THM_TCON_CUR_TMP__MCM_EN_MASK                                                                         0x00100000L
-#define THM_TCON_CUR_TMP__CUR_TEMP_MASK                                                                       0xFFE00000L
-//THM_TCON_HTC
-#define THM_TCON_HTC__HTC_EN__SHIFT                                                                           0x0
-#define THM_TCON_HTC__EXTERNAL_PROCHOT__SHIFT                                                                 0x2
-#define THM_TCON_HTC__INTERNAL_PROCHOT__SHIFT                                                                 0x3
-#define THM_TCON_HTC__HTC_ACTIVE__SHIFT                                                                       0x4
-#define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT                                                                   0x5
-#define THM_TCON_HTC__HTC_DIAG__SHIFT                                                                         0x8
-#define THM_TCON_HTC__DIS_PROCHOT_PIN__SHIFT                                                                  0x9
-#define THM_TCON_HTC__HTC_TO_IH_EN__SHIFT                                                                     0xa
-#define THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT                                                                 0xb
-#define THM_TCON_HTC__PROCHOT_EVENT_SRC__SHIFT                                                                0xc
-#define THM_TCON_HTC__HTC_TMP_LMT__SHIFT                                                                      0x10
-#define THM_TCON_HTC__HTC_HYST_LMT__SHIFT                                                                     0x17
-#define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT                                                                     0x1b
-#define THM_TCON_HTC__HTC_EN_MASK                                                                             0x00000001L
-#define THM_TCON_HTC__EXTERNAL_PROCHOT_MASK                                                                   0x00000004L
-#define THM_TCON_HTC__INTERNAL_PROCHOT_MASK                                                                   0x00000008L
-#define THM_TCON_HTC__HTC_ACTIVE_MASK                                                                         0x00000010L
-#define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK                                                                     0x00000020L
-#define THM_TCON_HTC__HTC_DIAG_MASK                                                                           0x00000100L
-#define THM_TCON_HTC__DIS_PROCHOT_PIN_MASK                                                                    0x00000200L
-#define THM_TCON_HTC__HTC_TO_IH_EN_MASK                                                                       0x00000400L
-#define THM_TCON_HTC__PROCHOT_TO_IH_EN_MASK                                                                   0x00000800L
-#define THM_TCON_HTC__PROCHOT_EVENT_SRC_MASK                                                                  0x00007000L
-#define THM_TCON_HTC__HTC_TMP_LMT_MASK                                                                        0x007F0000L
-#define THM_TCON_HTC__HTC_HYST_LMT_MASK                                                                       0x07800000L
-#define THM_TCON_HTC__HTC_SLEW_SEL_MASK                                                                       0x18000000L
-//THM_TCON_THERM_TRIP
-#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT                                                          0x0
-#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT                                                                  0x1
-#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT                                                    0x2
-#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT                                                            0x3
-#define THM_TCON_THERM_TRIP__RSVD2__SHIFT                                                                     0x4
-#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT                                                               0x5
-#define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT                                                              0x6
-#define THM_TCON_THERM_TRIP__RSVD3__SHIFT                                                                     0xe
-#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT                                                               0x1f
-#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK                                                            0x00000001L
-#define THM_TCON_THERM_TRIP__THERM_TP_MASK                                                                    0x00000002L
-#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK                                                      0x00000004L
-#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK                                                              0x00000008L
-#define THM_TCON_THERM_TRIP__RSVD2_MASK                                                                       0x00000010L
-#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK                                                                 0x00000020L
-#define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK                                                                0x00003FC0L
-#define THM_TCON_THERM_TRIP__RSVD3_MASK                                                                       0x7FFFC000L
-#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK                                                                 0x80000000L
-//THM_GPIO_PROCHOT_CTRL
-#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL__SHIFT                                                                0x0
-#define THM_GPIO_PROCHOT_CTRL__PD__SHIFT                                                                      0x1
-#define THM_GPIO_PROCHOT_CTRL__PU__SHIFT                                                                      0x2
-#define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT                                                                  0x3
-#define THM_GPIO_PROCHOT_CTRL__S0__SHIFT                                                                      0x4
-#define THM_GPIO_PROCHOT_CTRL__S1__SHIFT                                                                      0x5
-#define THM_GPIO_PROCHOT_CTRL__RXEN__SHIFT                                                                    0x6
-#define THM_GPIO_PROCHOT_CTRL__RXSEL0__SHIFT                                                                  0x7
-#define THM_GPIO_PROCHOT_CTRL__RXSEL1__SHIFT                                                                  0x8
-#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT                                                             0x10
-#define THM_GPIO_PROCHOT_CTRL__OE__SHIFT                                                                      0x11
-#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT                                                              0x12
-#define THM_GPIO_PROCHOT_CTRL__A__SHIFT                                                                       0x13
-#define THM_GPIO_PROCHOT_CTRL__Y__SHIFT                                                                       0x1f
-#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL_MASK                                                                  0x00000001L
-#define THM_GPIO_PROCHOT_CTRL__PD_MASK                                                                        0x00000002L
-#define THM_GPIO_PROCHOT_CTRL__PU_MASK                                                                        0x00000004L
-#define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK                                                                    0x00000008L
-#define THM_GPIO_PROCHOT_CTRL__S0_MASK                                                                        0x00000010L
-#define THM_GPIO_PROCHOT_CTRL__S1_MASK                                                                        0x00000020L
-#define THM_GPIO_PROCHOT_CTRL__RXEN_MASK                                                                      0x00000040L
-#define THM_GPIO_PROCHOT_CTRL__RXSEL0_MASK                                                                    0x00000080L
-#define THM_GPIO_PROCHOT_CTRL__RXSEL1_MASK                                                                    0x00000100L
-#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK                                                               0x00010000L
-#define THM_GPIO_PROCHOT_CTRL__OE_MASK                                                                        0x00020000L
-#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK                                                                0x00040000L
-#define THM_GPIO_PROCHOT_CTRL__A_MASK                                                                         0x00080000L
-#define THM_GPIO_PROCHOT_CTRL__Y_MASK                                                                         0x80000000L
-//THM_GPIO_THERMTRIP_CTRL
-#define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL__SHIFT                                                              0x0
-#define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT                                                                    0x1
-#define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT                                                                    0x2
-#define THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT                                                                0x3
-#define THM_GPIO_THERMTRIP_CTRL__S0__SHIFT                                                                    0x4
-#define THM_GPIO_THERMTRIP_CTRL__S1__SHIFT                                                                    0x5
-#define THM_GPIO_THERMTRIP_CTRL__RXEN__SHIFT                                                                  0x6
-#define THM_GPIO_THERMTRIP_CTRL__RXSEL0__SHIFT                                                                0x7
-#define THM_GPIO_THERMTRIP_CTRL__RXSEL1__SHIFT                                                                0x8
-#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT                                                           0x10
-#define THM_GPIO_THERMTRIP_CTRL__OE__SHIFT                                                                    0x11
-#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT                                                            0x12
-#define THM_GPIO_THERMTRIP_CTRL__A__SHIFT                                                                     0x13
-#define THM_GPIO_THERMTRIP_CTRL__CTFEN__SHIFT                                                                 0x14
-#define THM_GPIO_THERMTRIP_CTRL__Y__SHIFT                                                                     0x1f
-#define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL_MASK                                                                0x00000001L
-#define THM_GPIO_THERMTRIP_CTRL__PD_MASK                                                                      0x00000002L
-#define THM_GPIO_THERMTRIP_CTRL__PU_MASK                                                                      0x00000004L
-#define THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK                                                                  0x00000008L
-#define THM_GPIO_THERMTRIP_CTRL__S0_MASK                                                                      0x00000010L
-#define THM_GPIO_THERMTRIP_CTRL__S1_MASK                                                                      0x00000020L
-#define THM_GPIO_THERMTRIP_CTRL__RXEN_MASK                                                                    0x00000040L
-#define THM_GPIO_THERMTRIP_CTRL__RXSEL0_MASK                                                                  0x00000080L
-#define THM_GPIO_THERMTRIP_CTRL__RXSEL1_MASK                                                                  0x00000100L
-#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK                                                             0x00010000L
-#define THM_GPIO_THERMTRIP_CTRL__OE_MASK                                                                      0x00020000L
-#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK                                                              0x00040000L
-#define THM_GPIO_THERMTRIP_CTRL__A_MASK                                                                       0x00080000L
-#define THM_GPIO_THERMTRIP_CTRL__CTFEN_MASK                                                                   0x00100000L
-#define THM_GPIO_THERMTRIP_CTRL__Y_MASK                                                                       0x80000000L
-//THM_GPIO_PWM_CTRL
-#define THM_GPIO_PWM_CTRL__TXIMPSEL__SHIFT                                                                    0x0
-#define THM_GPIO_PWM_CTRL__PD__SHIFT                                                                          0x1
-#define THM_GPIO_PWM_CTRL__PU__SHIFT                                                                          0x2
-#define THM_GPIO_PWM_CTRL__SCHMEN__SHIFT                                                                      0x3
-#define THM_GPIO_PWM_CTRL__S0__SHIFT                                                                          0x4
-#define THM_GPIO_PWM_CTRL__S1__SHIFT                                                                          0x5
-#define THM_GPIO_PWM_CTRL__RXEN__SHIFT                                                                        0x6
-#define THM_GPIO_PWM_CTRL__RXSEL0__SHIFT                                                                      0x7
-#define THM_GPIO_PWM_CTRL__RXSEL1__SHIFT                                                                      0x8
-#define THM_GPIO_PWM_CTRL__OE_OVERRIDE__SHIFT                                                                 0x10
-#define THM_GPIO_PWM_CTRL__OE__SHIFT                                                                          0x11
-#define THM_GPIO_PWM_CTRL__A_OVERRIDE__SHIFT                                                                  0x12
-#define THM_GPIO_PWM_CTRL__A__SHIFT                                                                           0x13
-#define THM_GPIO_PWM_CTRL__Y__SHIFT                                                                           0x1f
-#define THM_GPIO_PWM_CTRL__TXIMPSEL_MASK                                                                      0x00000001L
-#define THM_GPIO_PWM_CTRL__PD_MASK                                                                            0x00000002L
-#define THM_GPIO_PWM_CTRL__PU_MASK                                                                            0x00000004L
-#define THM_GPIO_PWM_CTRL__SCHMEN_MASK                                                                        0x00000008L
-#define THM_GPIO_PWM_CTRL__S0_MASK                                                                            0x00000010L
-#define THM_GPIO_PWM_CTRL__S1_MASK                                                                            0x00000020L
-#define THM_GPIO_PWM_CTRL__RXEN_MASK                                                                          0x00000040L
-#define THM_GPIO_PWM_CTRL__RXSEL0_MASK                                                                        0x00000080L
-#define THM_GPIO_PWM_CTRL__RXSEL1_MASK                                                                        0x00000100L
-#define THM_GPIO_PWM_CTRL__OE_OVERRIDE_MASK                                                                   0x00010000L
-#define THM_GPIO_PWM_CTRL__OE_MASK                                                                            0x00020000L
-#define THM_GPIO_PWM_CTRL__A_OVERRIDE_MASK                                                                    0x00040000L
-#define THM_GPIO_PWM_CTRL__A_MASK                                                                             0x00080000L
-#define THM_GPIO_PWM_CTRL__Y_MASK                                                                             0x80000000L
-//THM_GPIO_TACHIN_CTRL
-#define THM_GPIO_TACHIN_CTRL__TXIMPSEL__SHIFT                                                                 0x0
-#define THM_GPIO_TACHIN_CTRL__PD__SHIFT                                                                       0x1
-#define THM_GPIO_TACHIN_CTRL__PU__SHIFT                                                                       0x2
-#define THM_GPIO_TACHIN_CTRL__SCHMEN__SHIFT                                                                   0x3
-#define THM_GPIO_TACHIN_CTRL__S0__SHIFT                                                                       0x4
-#define THM_GPIO_TACHIN_CTRL__S1__SHIFT                                                                       0x5
-#define THM_GPIO_TACHIN_CTRL__RXEN__SHIFT                                                                     0x6
-#define THM_GPIO_TACHIN_CTRL__RXSEL0__SHIFT                                                                   0x7
-#define THM_GPIO_TACHIN_CTRL__RXSEL1__SHIFT                                                                   0x8
-#define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE__SHIFT                                                              0x10
-#define THM_GPIO_TACHIN_CTRL__OE__SHIFT                                                                       0x11
-#define THM_GPIO_TACHIN_CTRL__A_OVERRIDE__SHIFT                                                               0x12
-#define THM_GPIO_TACHIN_CTRL__A__SHIFT                                                                        0x13
-#define THM_GPIO_TACHIN_CTRL__Y__SHIFT                                                                        0x1f
-#define THM_GPIO_TACHIN_CTRL__TXIMPSEL_MASK                                                                   0x00000001L
-#define THM_GPIO_TACHIN_CTRL__PD_MASK                                                                         0x00000002L
-#define THM_GPIO_TACHIN_CTRL__PU_MASK                                                                         0x00000004L
-#define THM_GPIO_TACHIN_CTRL__SCHMEN_MASK                                                                     0x00000008L
-#define THM_GPIO_TACHIN_CTRL__S0_MASK                                                                         0x00000010L
-#define THM_GPIO_TACHIN_CTRL__S1_MASK                                                                         0x00000020L
-#define THM_GPIO_TACHIN_CTRL__RXEN_MASK                                                                       0x00000040L
-#define THM_GPIO_TACHIN_CTRL__RXSEL0_MASK                                                                     0x00000080L
-#define THM_GPIO_TACHIN_CTRL__RXSEL1_MASK                                                                     0x00000100L
-#define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE_MASK                                                                0x00010000L
-#define THM_GPIO_TACHIN_CTRL__OE_MASK                                                                         0x00020000L
-#define THM_GPIO_TACHIN_CTRL__A_OVERRIDE_MASK                                                                 0x00040000L
-#define THM_GPIO_TACHIN_CTRL__A_MASK                                                                          0x00080000L
-#define THM_GPIO_TACHIN_CTRL__Y_MASK                                                                          0x80000000L
-//THM_GPIO_PUMPOUT_CTRL
-#define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL__SHIFT                                                                0x0
-#define THM_GPIO_PUMPOUT_CTRL__PD__SHIFT                                                                      0x1
-#define THM_GPIO_PUMPOUT_CTRL__PU__SHIFT                                                                      0x2
-#define THM_GPIO_PUMPOUT_CTRL__SCHMEN__SHIFT                                                                  0x3
-#define THM_GPIO_PUMPOUT_CTRL__S0__SHIFT                                                                      0x4
-#define THM_GPIO_PUMPOUT_CTRL__S1__SHIFT                                                                      0x5
-#define THM_GPIO_PUMPOUT_CTRL__RXEN__SHIFT                                                                    0x6
-#define THM_GPIO_PUMPOUT_CTRL__RXSEL0__SHIFT                                                                  0x7
-#define THM_GPIO_PUMPOUT_CTRL__RXSEL1__SHIFT                                                                  0x8
-#define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE__SHIFT                                                             0x10
-#define THM_GPIO_PUMPOUT_CTRL__OE__SHIFT                                                                      0x11
-#define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE__SHIFT                                                              0x12
-#define THM_GPIO_PUMPOUT_CTRL__A__SHIFT                                                                       0x13
-#define THM_GPIO_PUMPOUT_CTRL__Y__SHIFT                                                                       0x1f
-#define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL_MASK                                                                  0x00000001L
-#define THM_GPIO_PUMPOUT_CTRL__PD_MASK                                                                        0x00000002L
-#define THM_GPIO_PUMPOUT_CTRL__PU_MASK                                                                        0x00000004L
-#define THM_GPIO_PUMPOUT_CTRL__SCHMEN_MASK                                                                    0x00000008L
-#define THM_GPIO_PUMPOUT_CTRL__S0_MASK                                                                        0x00000010L
-#define THM_GPIO_PUMPOUT_CTRL__S1_MASK                                                                        0x00000020L
-#define THM_GPIO_PUMPOUT_CTRL__RXEN_MASK                                                                      0x00000040L
-#define THM_GPIO_PUMPOUT_CTRL__RXSEL0_MASK                                                                    0x00000080L
-#define THM_GPIO_PUMPOUT_CTRL__RXSEL1_MASK                                                                    0x00000100L
-#define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE_MASK                                                               0x00010000L
-#define THM_GPIO_PUMPOUT_CTRL__OE_MASK                                                                        0x00020000L
-#define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE_MASK                                                                0x00040000L
-#define THM_GPIO_PUMPOUT_CTRL__A_MASK                                                                         0x00080000L
-#define THM_GPIO_PUMPOUT_CTRL__Y_MASK                                                                         0x80000000L
-//THM_GPIO_PUMPIN_CTRL
-#define THM_GPIO_PUMPIN_CTRL__TXIMPSEL__SHIFT                                                                 0x0
-#define THM_GPIO_PUMPIN_CTRL__PD__SHIFT                                                                       0x1
-#define THM_GPIO_PUMPIN_CTRL__PU__SHIFT                                                                       0x2
-#define THM_GPIO_PUMPIN_CTRL__SCHMEN__SHIFT                                                                   0x3
-#define THM_GPIO_PUMPIN_CTRL__S0__SHIFT                                                                       0x4
-#define THM_GPIO_PUMPIN_CTRL__S1__SHIFT                                                                       0x5
-#define THM_GPIO_PUMPIN_CTRL__RXEN__SHIFT                                                                     0x6
-#define THM_GPIO_PUMPIN_CTRL__RXSEL0__SHIFT                                                                   0x7
-#define THM_GPIO_PUMPIN_CTRL__RXSEL1__SHIFT                                                                   0x8
-#define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE__SHIFT                                                              0x10
-#define THM_GPIO_PUMPIN_CTRL__OE__SHIFT                                                                       0x11
-#define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE__SHIFT                                                               0x12
-#define THM_GPIO_PUMPIN_CTRL__A__SHIFT                                                                        0x13
-#define THM_GPIO_PUMPIN_CTRL__Y__SHIFT                                                                        0x1f
-#define THM_GPIO_PUMPIN_CTRL__TXIMPSEL_MASK                                                                   0x00000001L
-#define THM_GPIO_PUMPIN_CTRL__PD_MASK                                                                         0x00000002L
-#define THM_GPIO_PUMPIN_CTRL__PU_MASK                                                                         0x00000004L
-#define THM_GPIO_PUMPIN_CTRL__SCHMEN_MASK                                                                     0x00000008L
-#define THM_GPIO_PUMPIN_CTRL__S0_MASK                                                                         0x00000010L
-#define THM_GPIO_PUMPIN_CTRL__S1_MASK                                                                         0x00000020L
-#define THM_GPIO_PUMPIN_CTRL__RXEN_MASK                                                                       0x00000040L
-#define THM_GPIO_PUMPIN_CTRL__RXSEL0_MASK                                                                     0x00000080L
-#define THM_GPIO_PUMPIN_CTRL__RXSEL1_MASK                                                                     0x00000100L
-#define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE_MASK                                                                0x00010000L
-#define THM_GPIO_PUMPIN_CTRL__OE_MASK                                                                         0x00020000L
-#define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE_MASK                                                                 0x00040000L
-#define THM_GPIO_PUMPIN_CTRL__A_MASK                                                                          0x00080000L
-#define THM_GPIO_PUMPIN_CTRL__Y_MASK                                                                          0x80000000L
-//THM_THERMAL_INT_ENA
-#define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT                                                            0x0
-#define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT                                                            0x1
-#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT                                                         0x2
-#define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT                                                            0x3
-#define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT                                                            0x4
-#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT                                                         0x5
-#define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK                                                              0x00000001L
-#define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK                                                              0x00000002L
-#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK                                                           0x00000004L
-#define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK                                                              0x00000008L
-#define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK                                                              0x00000010L
-#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK                                                           0x00000020L
-//THM_THERMAL_INT_CTRL
-#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT                                                           0x0
-#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT                                                           0x8
-#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD__SHIFT                                                           0x10
-#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT                                                          0x18
-#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT                                                          0x19
-#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT                                                       0x1a
-#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK__SHIFT                                                       0x1b
-#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT                                                          0x1c
-#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT                                                            0x1d
-#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK                                                             0x000000FFL
-#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK                                                             0x0000FF00L
-#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD_MASK                                                             0x00FF0000L
-#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK                                                            0x01000000L
-#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK                                                            0x02000000L
-#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK                                                         0x04000000L
-#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK_MASK                                                         0x08000000L
-#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK                                                            0x10000000L
-#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK                                                              0xE0000000L
-//THM_THERMAL_INT_STATUS
-#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT                                                      0x0
-#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT                                                      0x1
-#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT                                                   0x2
-#define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT__SHIFT                                                   0x3
-#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK                                                        0x00000001L
-#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK                                                        0x00000002L
-#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK                                                     0x00000004L
-#define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT_MASK                                                     0x00000008L
-//THM_TMON0_RDIL0_DATA
-#define THM_TMON0_RDIL0_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIL0_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIL0_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIL0_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIL0_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIL1_DATA
-#define THM_TMON0_RDIL1_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIL1_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIL1_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIL1_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIL1_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIL2_DATA
-#define THM_TMON0_RDIL2_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIL2_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIL2_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIL2_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIL2_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIL3_DATA
-#define THM_TMON0_RDIL3_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIL3_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIL3_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIL3_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIL3_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIL4_DATA
-#define THM_TMON0_RDIL4_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIL4_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIL4_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIL4_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIL4_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIL5_DATA
-#define THM_TMON0_RDIL5_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIL5_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIL5_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIL5_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIL5_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIL6_DATA
-#define THM_TMON0_RDIL6_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIL6_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIL6_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIL6_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIL6_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIL7_DATA
-#define THM_TMON0_RDIL7_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIL7_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIL7_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIL7_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIL7_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIL8_DATA
-#define THM_TMON0_RDIL8_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIL8_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIL8_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIL8_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIL8_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIL9_DATA
-#define THM_TMON0_RDIL9_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIL9_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIL9_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIL9_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIL9_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIL10_DATA
-#define THM_TMON0_RDIL10_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON0_RDIL10_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON0_RDIL10_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON0_RDIL10_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON0_RDIL10_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON0_RDIL11_DATA
-#define THM_TMON0_RDIL11_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON0_RDIL11_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON0_RDIL11_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON0_RDIL11_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON0_RDIL11_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON0_RDIL12_DATA
-#define THM_TMON0_RDIL12_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON0_RDIL12_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON0_RDIL12_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON0_RDIL12_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON0_RDIL12_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON0_RDIL13_DATA
-#define THM_TMON0_RDIL13_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON0_RDIL13_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON0_RDIL13_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON0_RDIL13_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON0_RDIL13_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON0_RDIL14_DATA
-#define THM_TMON0_RDIL14_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON0_RDIL14_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON0_RDIL14_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON0_RDIL14_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON0_RDIL14_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON0_RDIL15_DATA
-#define THM_TMON0_RDIL15_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON0_RDIL15_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON0_RDIL15_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON0_RDIL15_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON0_RDIL15_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON0_RDIR0_DATA
-#define THM_TMON0_RDIR0_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIR0_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIR0_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIR0_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIR0_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIR1_DATA
-#define THM_TMON0_RDIR1_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIR1_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIR1_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIR1_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIR1_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIR2_DATA
-#define THM_TMON0_RDIR2_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIR2_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIR2_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIR2_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIR2_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIR3_DATA
-#define THM_TMON0_RDIR3_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIR3_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIR3_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIR3_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIR3_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIR4_DATA
-#define THM_TMON0_RDIR4_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIR4_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIR4_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIR4_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIR4_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIR5_DATA
-#define THM_TMON0_RDIR5_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIR5_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIR5_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIR5_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIR5_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIR6_DATA
-#define THM_TMON0_RDIR6_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIR6_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIR6_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIR6_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIR6_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIR7_DATA
-#define THM_TMON0_RDIR7_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIR7_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIR7_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIR7_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIR7_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIR8_DATA
-#define THM_TMON0_RDIR8_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIR8_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIR8_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIR8_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIR8_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIR9_DATA
-#define THM_TMON0_RDIR9_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON0_RDIR9_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON0_RDIR9_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON0_RDIR9_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON0_RDIR9_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON0_RDIR10_DATA
-#define THM_TMON0_RDIR10_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON0_RDIR10_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON0_RDIR10_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON0_RDIR10_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON0_RDIR10_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON0_RDIR11_DATA
-#define THM_TMON0_RDIR11_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON0_RDIR11_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON0_RDIR11_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON0_RDIR11_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON0_RDIR11_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON0_RDIR12_DATA
-#define THM_TMON0_RDIR12_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON0_RDIR12_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON0_RDIR12_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON0_RDIR12_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON0_RDIR12_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON0_RDIR13_DATA
-#define THM_TMON0_RDIR13_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON0_RDIR13_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON0_RDIR13_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON0_RDIR13_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON0_RDIR13_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON0_RDIR14_DATA
-#define THM_TMON0_RDIR14_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON0_RDIR14_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON0_RDIR14_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON0_RDIR14_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON0_RDIR14_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON0_RDIR15_DATA
-#define THM_TMON0_RDIR15_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON0_RDIR15_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON0_RDIR15_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON0_RDIR15_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON0_RDIR15_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON0_INT_DATA
-#define THM_TMON0_INT_DATA__Z__SHIFT                                                                          0x0
-#define THM_TMON0_INT_DATA__VALID__SHIFT                                                                      0xb
-#define THM_TMON0_INT_DATA__TEMP__SHIFT                                                                       0xc
-#define THM_TMON0_INT_DATA__Z_MASK                                                                            0x000007FFL
-#define THM_TMON0_INT_DATA__VALID_MASK                                                                        0x00000800L
-#define THM_TMON0_INT_DATA__TEMP_MASK                                                                         0x00FFF000L
-//THM_TMON0_DEBUG
-#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT                                                                     0x0
-#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT                                                                       0x5
-#define THM_TMON0_DEBUG__DEBUG_RDI_MASK                                                                       0x0000001FL
-#define THM_TMON0_DEBUG__DEBUG_Z_MASK                                                                         0x0000FFE0L
-//THM_TMON1_RDIL0_DATA
-#define THM_TMON1_RDIL0_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIL0_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIL0_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIL0_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIL0_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIL1_DATA
-#define THM_TMON1_RDIL1_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIL1_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIL1_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIL1_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIL1_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIL2_DATA
-#define THM_TMON1_RDIL2_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIL2_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIL2_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIL2_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIL2_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIL3_DATA
-#define THM_TMON1_RDIL3_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIL3_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIL3_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIL3_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIL3_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIL4_DATA
-#define THM_TMON1_RDIL4_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIL4_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIL4_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIL4_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIL4_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIL5_DATA
-#define THM_TMON1_RDIL5_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIL5_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIL5_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIL5_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIL5_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIL6_DATA
-#define THM_TMON1_RDIL6_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIL6_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIL6_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIL6_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIL6_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIL7_DATA
-#define THM_TMON1_RDIL7_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIL7_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIL7_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIL7_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIL7_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIL8_DATA
-#define THM_TMON1_RDIL8_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIL8_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIL8_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIL8_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIL8_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIL9_DATA
-#define THM_TMON1_RDIL9_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIL9_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIL9_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIL9_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIL9_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIL10_DATA
-#define THM_TMON1_RDIL10_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON1_RDIL10_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON1_RDIL10_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON1_RDIL10_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON1_RDIL10_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON1_RDIL11_DATA
-#define THM_TMON1_RDIL11_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON1_RDIL11_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON1_RDIL11_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON1_RDIL11_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON1_RDIL11_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON1_RDIL12_DATA
-#define THM_TMON1_RDIL12_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON1_RDIL12_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON1_RDIL12_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON1_RDIL12_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON1_RDIL12_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON1_RDIL13_DATA
-#define THM_TMON1_RDIL13_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON1_RDIL13_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON1_RDIL13_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON1_RDIL13_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON1_RDIL13_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON1_RDIL14_DATA
-#define THM_TMON1_RDIL14_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON1_RDIL14_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON1_RDIL14_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON1_RDIL14_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON1_RDIL14_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON1_RDIL15_DATA
-#define THM_TMON1_RDIL15_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON1_RDIL15_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON1_RDIL15_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON1_RDIL15_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON1_RDIL15_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON1_RDIR0_DATA
-#define THM_TMON1_RDIR0_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIR0_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIR0_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIR0_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIR0_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIR1_DATA
-#define THM_TMON1_RDIR1_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIR1_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIR1_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIR1_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIR1_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIR2_DATA
-#define THM_TMON1_RDIR2_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIR2_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIR2_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIR2_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIR2_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIR3_DATA
-#define THM_TMON1_RDIR3_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIR3_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIR3_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIR3_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIR3_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIR4_DATA
-#define THM_TMON1_RDIR4_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIR4_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIR4_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIR4_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIR4_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIR5_DATA
-#define THM_TMON1_RDIR5_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIR5_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIR5_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIR5_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIR5_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIR6_DATA
-#define THM_TMON1_RDIR6_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIR6_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIR6_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIR6_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIR6_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIR7_DATA
-#define THM_TMON1_RDIR7_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIR7_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIR7_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIR7_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIR7_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIR8_DATA
-#define THM_TMON1_RDIR8_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIR8_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIR8_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIR8_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIR8_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIR9_DATA
-#define THM_TMON1_RDIR9_DATA__Z__SHIFT                                                                        0x0
-#define THM_TMON1_RDIR9_DATA__VALID__SHIFT                                                                    0xb
-#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT                                                                     0xc
-#define THM_TMON1_RDIR9_DATA__Z_MASK                                                                          0x000007FFL
-#define THM_TMON1_RDIR9_DATA__VALID_MASK                                                                      0x00000800L
-#define THM_TMON1_RDIR9_DATA__TEMP_MASK                                                                       0x00FFF000L
-//THM_TMON1_RDIR10_DATA
-#define THM_TMON1_RDIR10_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON1_RDIR10_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON1_RDIR10_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON1_RDIR10_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON1_RDIR10_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON1_RDIR11_DATA
-#define THM_TMON1_RDIR11_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON1_RDIR11_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON1_RDIR11_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON1_RDIR11_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON1_RDIR11_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON1_RDIR12_DATA
-#define THM_TMON1_RDIR12_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON1_RDIR12_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON1_RDIR12_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON1_RDIR12_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON1_RDIR12_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON1_RDIR13_DATA
-#define THM_TMON1_RDIR13_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON1_RDIR13_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON1_RDIR13_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON1_RDIR13_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON1_RDIR13_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON1_RDIR14_DATA
-#define THM_TMON1_RDIR14_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON1_RDIR14_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON1_RDIR14_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON1_RDIR14_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON1_RDIR14_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON1_RDIR15_DATA
-#define THM_TMON1_RDIR15_DATA__Z__SHIFT                                                                       0x0
-#define THM_TMON1_RDIR15_DATA__VALID__SHIFT                                                                   0xb
-#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT                                                                    0xc
-#define THM_TMON1_RDIR15_DATA__Z_MASK                                                                         0x000007FFL
-#define THM_TMON1_RDIR15_DATA__VALID_MASK                                                                     0x00000800L
-#define THM_TMON1_RDIR15_DATA__TEMP_MASK                                                                      0x00FFF000L
-//THM_TMON1_INT_DATA
-#define THM_TMON1_INT_DATA__Z__SHIFT                                                                          0x0
-#define THM_TMON1_INT_DATA__VALID__SHIFT                                                                      0xb
-#define THM_TMON1_INT_DATA__TEMP__SHIFT                                                                       0xc
-#define THM_TMON1_INT_DATA__Z_MASK                                                                            0x000007FFL
-#define THM_TMON1_INT_DATA__VALID_MASK                                                                        0x00000800L
-#define THM_TMON1_INT_DATA__TEMP_MASK                                                                         0x00FFF000L
-//THM_TMON1_DEBUG
-#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT                                                                     0x0
-#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT                                                                       0x5
-#define THM_TMON1_DEBUG__DEBUG_RDI_MASK                                                                       0x0000001FL
-#define THM_TMON1_DEBUG__DEBUG_Z_MASK                                                                         0x0000FFE0L
-//THM_DIE1_TEMP
-#define THM_DIE1_TEMP__TEMP__SHIFT                                                                            0x0
-#define THM_DIE1_TEMP__VALID__SHIFT                                                                           0xb
-#define THM_DIE1_TEMP__TEMP_MASK                                                                              0x000007FFL
-#define THM_DIE1_TEMP__VALID_MASK                                                                             0x00000800L
-//THM_DIE2_TEMP
-#define THM_DIE2_TEMP__TEMP__SHIFT                                                                            0x0
-#define THM_DIE2_TEMP__VALID__SHIFT                                                                           0xb
-#define THM_DIE2_TEMP__TEMP_MASK                                                                              0x000007FFL
-#define THM_DIE2_TEMP__VALID_MASK                                                                             0x00000800L
-//THM_DIE3_TEMP
-#define THM_DIE3_TEMP__TEMP__SHIFT                                                                            0x0
-#define THM_DIE3_TEMP__VALID__SHIFT                                                                           0xb
-#define THM_DIE3_TEMP__TEMP_MASK                                                                              0x000007FFL
-#define THM_DIE3_TEMP__VALID_MASK                                                                             0x00000800L
-//CG_MULT_THERMAL_CTRL
-#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT                                                                0x0
-#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT                                                                   0x4
-#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT                                                        0x9
-#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT                                                                 0x14
-#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK                                                                  0x0000000FL
-#define CG_MULT_THERMAL_CTRL__UNUSED_MASK                                                                     0x000001F0L
-#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK                                                          0x00000200L
-#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK                                                                   0x0FF00000L
-//CG_MULT_THERMAL_STATUS
-#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT                                                          0x0
-#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT                                                               0x9
-#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK                                                            0x000001FFL
-#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK                                                                 0x0003FE00L
-//THM_TMON0_COEFF
-#define THM_TMON0_COEFF__C_OFFSET__SHIFT                                                                      0x0
-#define THM_TMON0_COEFF__D__SHIFT                                                                             0xb
-#define THM_TMON0_COEFF__C_OFFSET_MASK                                                                        0x000007FFL
-#define THM_TMON0_COEFF__D_MASK                                                                               0x0003F800L
-//THM_TMON1_COEFF
-#define THM_TMON1_COEFF__C_OFFSET__SHIFT                                                                      0x0
-#define THM_TMON1_COEFF__D__SHIFT                                                                             0xb
-#define THM_TMON1_COEFF__C_OFFSET_MASK                                                                        0x000007FFL
-#define THM_TMON1_COEFF__D_MASK                                                                               0x0003F800L
-//CG_FDO_CTRL0
-#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT                                                                  0x0
-#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT                                                                  0x8
-#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT                                                                   0x10
-#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT                                                                   0x11
-#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT                                                                  0x17
-#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT                                                                     0x18
-#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK                                                                    0x000000FFL
-#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK                                                                    0x0000FF00L
-#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK                                                                     0x00010000L
-#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK                                                                     0x007E0000L
-#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK                                                                    0x00800000L
-#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK                                                                       0xFF000000L
-//CG_FDO_CTRL1
-#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT                                                                     0x0
-#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT                                                                        0x8
-#define CG_FDO_CTRL1__M__SHIFT                                                                                0x10
-#define CG_FDO_CTRL1__RESERVED__SHIFT                                                                         0x18
-#define CG_FDO_CTRL1__FMAX_DUTY100_MASK                                                                       0x000000FFL
-#define CG_FDO_CTRL1__FMIN_DUTY_MASK                                                                          0x0000FF00L
-#define CG_FDO_CTRL1__M_MASK                                                                                  0x00FF0000L
-#define CG_FDO_CTRL1__RESERVED_MASK                                                                           0x3F000000L
-//CG_FDO_CTRL2
-#define CG_FDO_CTRL2__TMIN__SHIFT                                                                             0x0
-#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT                                                                  0x8
-#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT                                                                     0xb
-#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT                                                                      0xe
-#define CG_FDO_CTRL2__TMAX__SHIFT                                                                             0x11
-#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT                                                               0x19
-#define CG_FDO_CTRL2__TMIN_MASK                                                                               0x000000FFL
-#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK                                                                    0x00000700L
-#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK                                                                       0x00003800L
-#define CG_FDO_CTRL2__TMIN_HYSTER_MASK                                                                        0x0001C000L
-#define CG_FDO_CTRL2__TMAX_MASK                                                                               0x01FE0000L
-#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK                                                                 0xFE000000L
-//CG_TACH_CTRL
-#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT                                                                     0x0
-#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT                                                                    0x3
-#define CG_TACH_CTRL__EDGE_PER_REV_MASK                                                                       0x00000007L
-#define CG_TACH_CTRL__TARGET_PERIOD_MASK                                                                      0xFFFFFFF8L
-//CG_TACH_STATUS
-#define CG_TACH_STATUS__TACH_PERIOD__SHIFT                                                                    0x0
-#define CG_TACH_STATUS__TACH_PERIOD_MASK                                                                      0xFFFFFFFFL
-//CG_THERMAL_STATUS
-#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT                                                                0x9
-#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK                                                                  0x0001FE00L
-//CG_PUMP_CTRL0
-#define CG_PUMP_CTRL0__PUMP_STATIC_DUTY__SHIFT                                                                0x0
-#define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY__SHIFT                                                                0x8
-#define CG_PUMP_CTRL0__PUMP_PWM_MANUAL__SHIFT                                                                 0x10
-#define CG_PUMP_CTRL0__PUMP_PWM_HYSTER__SHIFT                                                                 0x11
-#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN__SHIFT                                                                0x17
-#define CG_PUMP_CTRL0__PUMP_PWM_RAMP__SHIFT                                                                   0x18
-#define CG_PUMP_CTRL0__PUMP_STATIC_DUTY_MASK                                                                  0x000000FFL
-#define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY_MASK                                                                  0x0000FF00L
-#define CG_PUMP_CTRL0__PUMP_PWM_MANUAL_MASK                                                                   0x00010000L
-#define CG_PUMP_CTRL0__PUMP_PWM_HYSTER_MASK                                                                   0x007E0000L
-#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN_MASK                                                                  0x00800000L
-#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_MASK                                                                     0xFF000000L
-//CG_PUMP_CTRL1
-#define CG_PUMP_CTRL1__PMAX_DUTY100__SHIFT                                                                    0x0
-#define CG_PUMP_CTRL1__PMIN_DUTY__SHIFT                                                                       0x8
-#define CG_PUMP_CTRL1__M__SHIFT                                                                               0x10
-#define CG_PUMP_CTRL1__RESERVED__SHIFT                                                                        0x18
-#define CG_PUMP_CTRL1__PMAX_DUTY100_MASK                                                                      0x000000FFL
-#define CG_PUMP_CTRL1__PMIN_DUTY_MASK                                                                         0x0000FF00L
-#define CG_PUMP_CTRL1__M_MASK                                                                                 0x00FF0000L
-#define CG_PUMP_CTRL1__RESERVED_MASK                                                                          0x3F000000L
-//CG_PUMP_CTRL2
-#define CG_PUMP_CTRL2__TMIN__SHIFT                                                                            0x0
-#define CG_PUMP_CTRL2__PUMP_SPINUP_TIME__SHIFT                                                                0x8
-#define CG_PUMP_CTRL2__PUMP_PWM_MODE__SHIFT                                                                   0xb
-#define CG_PUMP_CTRL2__TMIN_HYSTER__SHIFT                                                                     0xe
-#define CG_PUMP_CTRL2__TMAX__SHIFT                                                                            0x11
-#define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE__SHIFT                                                              0x19
-#define CG_PUMP_CTRL2__TMIN_MASK                                                                              0x000000FFL
-#define CG_PUMP_CTRL2__PUMP_SPINUP_TIME_MASK                                                                  0x00000700L
-#define CG_PUMP_CTRL2__PUMP_PWM_MODE_MASK                                                                     0x00003800L
-#define CG_PUMP_CTRL2__TMIN_HYSTER_MASK                                                                       0x0001C000L
-#define CG_PUMP_CTRL2__TMAX_MASK                                                                              0x01FE0000L
-#define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE_MASK                                                                0xFE000000L
-//CG_PUMP_TACH_CTRL
-#define CG_PUMP_TACH_CTRL__EDGE_PER_REV__SHIFT                                                                0x0
-#define CG_PUMP_TACH_CTRL__TARGET_PERIOD__SHIFT                                                               0x3
-#define CG_PUMP_TACH_CTRL__EDGE_PER_REV_MASK                                                                  0x00000007L
-#define CG_PUMP_TACH_CTRL__TARGET_PERIOD_MASK                                                                 0xFFFFFFF8L
-//CG_PUMP_TACH_STATUS
-#define CG_PUMP_TACH_STATUS__TACH_PERIOD__SHIFT                                                               0x0
-#define CG_PUMP_TACH_STATUS__TACH_PERIOD_MASK                                                                 0xFFFFFFFFL
-//CG_PUMP_STATUS
-#define CG_PUMP_STATUS__PUMP_PWM_DUTY__SHIFT                                                                  0x9
-#define CG_PUMP_STATUS__PUMP_PWM_DUTY_MASK                                                                    0x0001FE00L
-//THM_TCON_LOCAL0
-#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT                                                               0x1
-#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT                                                               0x2
-#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK                                                                 0x00000002L
-#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK                                                                 0x00000004L
-//THM_TCON_LOCAL1
-#define THM_TCON_LOCAL1__Turn_Off_TMON0__SHIFT                                                                0x0
-#define THM_TCON_LOCAL1__Turn_Off_TMON1__SHIFT                                                                0x1
-#define THM_TCON_LOCAL1__PowerDownTmon0__SHIFT                                                                0x4
-#define THM_TCON_LOCAL1__PowerDownTmon1__SHIFT                                                                0x5
-#define THM_TCON_LOCAL1__Turn_Off_TMON0_MASK                                                                  0x00000001L
-#define THM_TCON_LOCAL1__Turn_Off_TMON1_MASK                                                                  0x00000002L
-#define THM_TCON_LOCAL1__PowerDownTmon0_MASK                                                                  0x00000010L
-#define THM_TCON_LOCAL1__PowerDownTmon1_MASK                                                                  0x00000020L
-//THM_TCON_LOCAL2
-#define THM_TCON_LOCAL2__TMON_init_delay__SHIFT                                                               0x0
-#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time__SHIFT                                                       0x2
-#define THM_TCON_LOCAL2__short_stagger_count__SHIFT                                                           0x5
-#define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT                                                           0x6
-#define THM_TCON_LOCAL2__temp_read_skip_scale__SHIFT                                                          0xa
-#define THM_TCON_LOCAL2__skip_scale_correction__SHIFT                                                         0xb
-#define THM_TCON_LOCAL2__TMON_init_delay_MASK                                                                 0x00000003L
-#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time_MASK                                                         0x0000000CL
-#define THM_TCON_LOCAL2__short_stagger_count_MASK                                                             0x00000020L
-#define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK                                                             0x00000040L
-#define THM_TCON_LOCAL2__temp_read_skip_scale_MASK                                                            0x00000400L
-#define THM_TCON_LOCAL2__skip_scale_correction_MASK                                                           0x00000800L
-//THM_TCON_LOCAL3
-#define THM_TCON_LOCAL3__Global_TMAX__SHIFT                                                                   0x0
-#define THM_TCON_LOCAL3__Global_TMAX_MASK                                                                     0x000007FFL
-//THM_TCON_LOCAL4
-#define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT                                                                0x0
-#define THM_TCON_LOCAL4__Global_TMAX_ID_MASK                                                                  0x000000FFL
-//THM_TCON_LOCAL5
-#define THM_TCON_LOCAL5__Global_TMIN__SHIFT                                                                   0x0
-#define THM_TCON_LOCAL5__Global_TMIN_MASK                                                                     0x000007FFL
-//THM_TCON_LOCAL6
-#define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT                                                                0x0
-#define THM_TCON_LOCAL6__Global_TMIN_ID_MASK                                                                  0x000000FFL
-//THM_TCON_LOCAL7
-#define THM_TCON_LOCAL7__THERMID__SHIFT                                                                       0x0
-#define THM_TCON_LOCAL7__THERMID_MASK                                                                         0x000000FFL
-//THM_TCON_LOCAL8
-#define THM_TCON_LOCAL8__THERMMAX__SHIFT                                                                      0x0
-#define THM_TCON_LOCAL8__THERMMAX_MASK                                                                        0x000007FFL
-//THM_TCON_LOCAL9
-#define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT                                                                  0x0
-#define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK                                                                    0x000007FFL
-//THM_TCON_LOCAL10
-#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT                                                           0x0
-#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK                                                             0x000000FFL
-//THM_TCON_LOCAL11
-#define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT                                                                 0x0
-#define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK                                                                   0x000007FFL
-//THM_TCON_LOCAL12
-#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT                                                           0x0
-#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK                                                             0x000000FFL
-//THM_TCON_LOCAL13
-#define THM_TCON_LOCAL13__boot_done__SHIFT                                                                    0x0
-#define THM_TCON_LOCAL13__boot_done_MASK                                                                      0x00000001L
-//THM_BACO_CNTL
-#define THM_BACO_CNTL__BACO_MODE__SHIFT                                                                       0x0
-#define THM_BACO_CNTL__BACO_ISO_EN__SHIFT                                                                     0x1
-#define THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT                                                              0x2
-#define THM_BACO_CNTL__BACO_RESET_EN__SHIFT                                                                   0x3
-#define THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT                                                             0x4
-#define THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT                                                                 0x5
-#define THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT                                                             0x6
-#define THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT                                                                 0x7
-#define THM_BACO_CNTL__BACO_EXIT__SHIFT                                                                       0x8
-#define THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT                                                                 0x9
-#define THM_BACO_CNTL__BACO_SB_AXI_FENCE__SHIFT                                                               0x1e
-#define THM_BACO_CNTL__SOC_DOMAIN_IDLE__SHIFT                                                                 0x1f
-#define THM_BACO_CNTL__BACO_MODE_MASK                                                                         0x00000001L
-#define THM_BACO_CNTL__BACO_ISO_EN_MASK                                                                       0x00000002L
-#define THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK                                                                0x00000004L
-#define THM_BACO_CNTL__BACO_RESET_EN_MASK                                                                     0x00000008L
-#define THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK                                                               0x00000010L
-#define THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK                                                                   0x00000020L
-#define THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK                                                               0x00000040L
-#define THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK                                                                   0x00000080L
-#define THM_BACO_CNTL__BACO_EXIT_MASK                                                                         0x00000100L
-#define THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK                                                                   0x00000200L
-#define THM_BACO_CNTL__BACO_SB_AXI_FENCE_MASK                                                                 0x40000000L
-#define THM_BACO_CNTL__SOC_DOMAIN_IDLE_MASK                                                                   0x80000000L
-//THM_BACO_TIMING0
-#define THM_BACO_TIMING0__BACO_ISO_EXIT_CNT__SHIFT                                                            0x0
-#define THM_BACO_TIMING0__BACO_PWROKRAW_EXIT_CNT__SHIFT                                                       0x8
-#define THM_BACO_TIMING0__BACO_RESET_EXIT_CNT__SHIFT                                                          0x10
-#define THM_BACO_TIMING0__BACO_VDCI_RESET_EXIT_CNT__SHIFT                                                     0x18
-#define THM_BACO_TIMING0__BACO_ISO_EXIT_CNT_MASK                                                              0x000000FFL
-#define THM_BACO_TIMING0__BACO_PWROKRAW_EXIT_CNT_MASK                                                         0x0000FF00L
-#define THM_BACO_TIMING0__BACO_RESET_EXIT_CNT_MASK                                                            0x00FF0000L
-#define THM_BACO_TIMING0__BACO_VDCI_RESET_EXIT_CNT_MASK                                                       0xFF000000L
-//THM_BACO_TIMING1
-#define THM_BACO_TIMING1__BACO_SMNCLK_EXIT_CNT__SHIFT                                                         0x0
-#define THM_BACO_TIMING1__BACO_FENCE_EXIT_CNT__SHIFT                                                          0x8
-#define THM_BACO_TIMING1__BACO_REFCLK_EXIT_CNT__SHIFT                                                         0x10
-#define THM_BACO_TIMING1__BACO_MODE_EXIT_CNT__SHIFT                                                           0x18
-#define THM_BACO_TIMING1__BACO_SMNCLK_EXIT_CNT_MASK                                                           0x000000FFL
-#define THM_BACO_TIMING1__BACO_FENCE_EXIT_CNT_MASK                                                            0x0000FF00L
-#define THM_BACO_TIMING1__BACO_REFCLK_EXIT_CNT_MASK                                                           0x00FF0000L
-#define THM_BACO_TIMING1__BACO_MODE_EXIT_CNT_MASK                                                             0xFF000000L
-//XTAL_CNTL
-#define XTAL_CNTL__PCIE_REFCLK_SWITCH__SHIFT                                                                  0x0
-#define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN__SHIFT                                                              0x4
-#define XTAL_CNTL__CORE_XTAL_PWDN__SHIFT                                                                      0x8
-#define XTAL_CNTL__OSC_GAIN_EN__SHIFT                                                                         0xc
-#define XTAL_CNTL__PCIE_REFCLK_SWITCH_MASK                                                                    0x00000001L
-#define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN_MASK                                                                0x00000010L
-#define XTAL_CNTL__CORE_XTAL_PWDN_MASK                                                                        0x00000100L
-#define XTAL_CNTL__OSC_GAIN_EN_MASK                                                                           0x00007000L
-//SBTSI_REMOTE_TEMP
-#define SBTSI_REMOTE_TEMP__RemoteTcenSensor__SHIFT                                                            0x0
-#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId__SHIFT                                                          0xb
-#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid__SHIFT                                                       0x13
-#define SBTSI_REMOTE_TEMP__RemoteTcenSensor_MASK                                                              0x000007FFL
-#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId_MASK                                                            0x0007F800L
-#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid_MASK                                                         0x00080000L
-//SBRMI_CONTROL
-#define SBRMI_CONTROL__READ_CMD_INT_DIS__SHIFT                                                                0x0
-#define SBRMI_CONTROL__DPD__SHIFT                                                                             0x1
-#define SBRMI_CONTROL__DbrdySts__SHIFT                                                                        0x2
-#define SBRMI_CONTROL__READ_CMD_INT_DIS_MASK                                                                  0x00000001L
-#define SBRMI_CONTROL__DPD_MASK                                                                               0x00000002L
-#define SBRMI_CONTROL__DbrdySts_MASK                                                                          0x00000004L
-//SBRMI_COMMAND
-#define SBRMI_COMMAND__Command__SHIFT                                                                         0x0
-#define SBRMI_COMMAND__WrDataLen__SHIFT                                                                       0x8
-#define SBRMI_COMMAND__RdDataLen__SHIFT                                                                       0x10
-#define SBRMI_COMMAND__CommandSent__SHIFT                                                                     0x18
-#define SBRMI_COMMAND__CommandNotSupported__SHIFT                                                             0x19
-#define SBRMI_COMMAND__CommandAborted__SHIFT                                                                  0x1a
-#define SBRMI_COMMAND__Status__SHIFT                                                                          0x1c
-#define SBRMI_COMMAND__Command_MASK                                                                           0x000000FFL
-#define SBRMI_COMMAND__WrDataLen_MASK                                                                         0x0000FF00L
-#define SBRMI_COMMAND__RdDataLen_MASK                                                                         0x00FF0000L
-#define SBRMI_COMMAND__CommandSent_MASK                                                                       0x01000000L
-#define SBRMI_COMMAND__CommandNotSupported_MASK                                                               0x02000000L
-#define SBRMI_COMMAND__CommandAborted_MASK                                                                    0x04000000L
-#define SBRMI_COMMAND__Status_MASK                                                                            0xF0000000L
-//SBRMI_WRITE_DATA0
-#define SBRMI_WRITE_DATA0__WrByte0__SHIFT                                                                     0x0
-#define SBRMI_WRITE_DATA0__WrByte1__SHIFT                                                                     0x8
-#define SBRMI_WRITE_DATA0__WrByte2__SHIFT                                                                     0x10
-#define SBRMI_WRITE_DATA0__WrByte3__SHIFT                                                                     0x18
-#define SBRMI_WRITE_DATA0__WrByte0_MASK                                                                       0x000000FFL
-#define SBRMI_WRITE_DATA0__WrByte1_MASK                                                                       0x0000FF00L
-#define SBRMI_WRITE_DATA0__WrByte2_MASK                                                                       0x00FF0000L
-#define SBRMI_WRITE_DATA0__WrByte3_MASK                                                                       0xFF000000L
-//SBRMI_WRITE_DATA1
-#define SBRMI_WRITE_DATA1__WrByte4__SHIFT                                                                     0x0
-#define SBRMI_WRITE_DATA1__WrByte5__SHIFT                                                                     0x8
-#define SBRMI_WRITE_DATA1__WrByte6__SHIFT                                                                     0x10
-#define SBRMI_WRITE_DATA1__WrByte7__SHIFT                                                                     0x18
-#define SBRMI_WRITE_DATA1__WrByte4_MASK                                                                       0x000000FFL
-#define SBRMI_WRITE_DATA1__WrByte5_MASK                                                                       0x0000FF00L
-#define SBRMI_WRITE_DATA1__WrByte6_MASK                                                                       0x00FF0000L
-#define SBRMI_WRITE_DATA1__WrByte7_MASK                                                                       0xFF000000L
-//SBRMI_WRITE_DATA2
-#define SBRMI_WRITE_DATA2__WrByte8__SHIFT                                                                     0x0
-#define SBRMI_WRITE_DATA2__WrByte9__SHIFT                                                                     0x8
-#define SBRMI_WRITE_DATA2__WrByte10__SHIFT                                                                    0x10
-#define SBRMI_WRITE_DATA2__WrByte11__SHIFT                                                                    0x18
-#define SBRMI_WRITE_DATA2__WrByte8_MASK                                                                       0x000000FFL
-#define SBRMI_WRITE_DATA2__WrByte9_MASK                                                                       0x0000FF00L
-#define SBRMI_WRITE_DATA2__WrByte10_MASK                                                                      0x00FF0000L
-#define SBRMI_WRITE_DATA2__WrByte11_MASK                                                                      0xFF000000L
-//SBRMI_READ_DATA0
-#define SBRMI_READ_DATA0__RdByte0__SHIFT                                                                      0x0
-#define SBRMI_READ_DATA0__RdByte1__SHIFT                                                                      0x8
-#define SBRMI_READ_DATA0__RdByte2__SHIFT                                                                      0x10
-#define SBRMI_READ_DATA0__RdByte3__SHIFT                                                                      0x18
-#define SBRMI_READ_DATA0__RdByte0_MASK                                                                        0x000000FFL
-#define SBRMI_READ_DATA0__RdByte1_MASK                                                                        0x0000FF00L
-#define SBRMI_READ_DATA0__RdByte2_MASK                                                                        0x00FF0000L
-#define SBRMI_READ_DATA0__RdByte3_MASK                                                                        0xFF000000L
-//SBRMI_READ_DATA1
-#define SBRMI_READ_DATA1__RdByte4__SHIFT                                                                      0x0
-#define SBRMI_READ_DATA1__RdByte5__SHIFT                                                                      0x8
-#define SBRMI_READ_DATA1__RdByte6__SHIFT                                                                      0x10
-#define SBRMI_READ_DATA1__RdByte7__SHIFT                                                                      0x18
-#define SBRMI_READ_DATA1__RdByte4_MASK                                                                        0x000000FFL
-#define SBRMI_READ_DATA1__RdByte5_MASK                                                                        0x0000FF00L
-#define SBRMI_READ_DATA1__RdByte6_MASK                                                                        0x00FF0000L
-#define SBRMI_READ_DATA1__RdByte7_MASK                                                                        0xFF000000L
-//SBRMI_CORE_EN_NUMBER
-#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum__SHIFT                                                           0x0
-#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum_MASK                                                             0x0000007FL
-//SBRMI_CORE_EN_STATUS0
-#define SBRMI_CORE_EN_STATUS0__CoreEnStat0__SHIFT                                                             0x0
-#define SBRMI_CORE_EN_STATUS0__CoreEnStat0_MASK                                                               0xFFFFFFFFL
-//SBRMI_CORE_EN_STATUS1
-#define SBRMI_CORE_EN_STATUS1__CoreEnStat1__SHIFT                                                             0x0
-#define SBRMI_CORE_EN_STATUS1__CoreEnStat1_MASK                                                               0xFFFFFFFFL
-//SBRMI_APIC_STATUS0
-#define SBRMI_APIC_STATUS0__APICStat0__SHIFT                                                                  0x0
-#define SBRMI_APIC_STATUS0__APICStat0_MASK                                                                    0xFFFFFFFFL
-//SBRMI_APIC_STATUS1
-#define SBRMI_APIC_STATUS1__APICStat1__SHIFT                                                                  0x0
-#define SBRMI_APIC_STATUS1__APICStat1_MASK                                                                    0xFFFFFFFFL
-//SBRMI_MCE_STATUS0
-#define SBRMI_MCE_STATUS0__MceStat0__SHIFT                                                                    0x0
-#define SBRMI_MCE_STATUS0__MceStat0_MASK                                                                      0xFFFFFFFFL
-//SBRMI_MCE_STATUS1
-#define SBRMI_MCE_STATUS1__MceStat1__SHIFT                                                                    0x0
-#define SBRMI_MCE_STATUS1__MceStat1_MASK                                                                      0xFFFFFFFFL
-//SMBUS_CNTL0
-#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE__SHIFT                                                     0x0
-#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR__SHIFT                                                              0x1
-#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE__SHIFT                                                                0x8
-#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES__SHIFT                                                          0x10
-#define SMBUS_CNTL0__THM_READY__SHIFT                                                                         0x14
-#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE_MASK                                                       0x00000001L
-#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_MASK                                                                0x000000FEL
-#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE_MASK                                                                  0x0000FF00L
-#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES_MASK                                                            0x00070000L
-#define SMBUS_CNTL0__THM_READY_MASK                                                                           0x00100000L
-//SMBUS_CNTL1
-#define SMBUS_CNTL1__SMB_TIMEOUT_EN__SHIFT                                                                    0x0
-#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN__SHIFT                                                                 0x1
-#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN__SHIFT                                                                 0x9
-#define SMBUS_CNTL1__SMB_TIMEOUT_EN_MASK                                                                      0x00000001L
-#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN_MASK                                                                   0x000001FEL
-#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN_MASK                                                                   0x0001FE00L
-//SMBUS_BLKWR_CMD_CTRL0
-#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0__SHIFT                                                         0x0
-#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1__SHIFT                                                         0x8
-#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2__SHIFT                                                         0x10
-#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3__SHIFT                                                         0x18
-#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0_MASK                                                           0x000000FFL
-#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1_MASK                                                           0x0000FF00L
-#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2_MASK                                                           0x00FF0000L
-#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3_MASK                                                           0xFF000000L
-//SMBUS_BLKWR_CMD_CTRL1
-#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4__SHIFT                                                         0x0
-#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5__SHIFT                                                         0x8
-#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6__SHIFT                                                         0x10
-#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7__SHIFT                                                         0x18
-#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4_MASK                                                           0x000000FFL
-#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5_MASK                                                           0x0000FF00L
-#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6_MASK                                                           0x00FF0000L
-#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7_MASK                                                           0xFF000000L
-//SMBUS_BLKRD_CMD_CTRL0
-#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0__SHIFT                                                         0x0
-#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1__SHIFT                                                         0x8
-#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2__SHIFT                                                         0x10
-#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3__SHIFT                                                         0x18
-#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0_MASK                                                           0x000000FFL
-#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1_MASK                                                           0x0000FF00L
-#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2_MASK                                                           0x00FF0000L
-#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3_MASK                                                           0xFF000000L
-//SMBUS_BLKRD_CMD_CTRL1
-#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4__SHIFT                                                         0x0
-#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5__SHIFT                                                         0x8
-#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6__SHIFT                                                         0x10
-#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7__SHIFT                                                         0x18
-#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4_MASK                                                           0x000000FFL
-#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5_MASK                                                           0x0000FF00L
-#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6_MASK                                                           0x00FF0000L
-#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7_MASK                                                           0xFF000000L
-//SMBUS_TIMING_CNTL0
-#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN__SHIFT                                                         0x0
-#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN__SHIFT                                            0x16
-#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN_MASK                                                           0x003FFFFFL
-#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN_MASK                                              0x3FC00000L
-//SMBUS_TIMING_CNTL1
-#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN__SHIFT                                                  0x0
-#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT                                                   0x5
-#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN__SHIFT                                           0xb
-#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN__SHIFT                                                        0x14
-#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN_MASK                                                    0x0000001FL
-#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK                                                     0x000007E0L
-#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN_MASK                                             0x000FF800L
-#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN_MASK                                                          0x3FF00000L
-//SMBUS_TIMING_CNTL2
-#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN__SHIFT                                                  0x0
-#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN__SHIFT                                                   0xd
-#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN_MASK                                                    0x00001FFFL
-#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN_MASK                                                     0x07FFE000L
-//SMBUS_TRIGGER_CNTL
-#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER__SHIFT                                                     0x0
-#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER__SHIFT                                                     0x8
-#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER_MASK                                                       0x00000001L
-#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER_MASK                                                       0x00000100L
-//SMBUS_UDID_CNTL0
-#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED__SHIFT                                                            0x0
-#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN__SHIFT                                                       0x1f
-#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED_MASK                                                              0x7FFFFFFFL
-#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN_MASK                                                         0x80000000L
-//SMBUS_UDID_CNTL1
-#define SMBUS_UDID_CNTL1__SMB_UDID_31_0__SHIFT                                                                0x0
-#define SMBUS_UDID_CNTL1__SMB_UDID_31_0_MASK                                                                  0xFFFFFFFFL
-//SMBUS_UDID_CNTL2
-#define SMBUS_UDID_CNTL2__PEC_SUPPORTED__SHIFT                                                                0x0
-#define SMBUS_UDID_CNTL2__UDID_VERSION__SHIFT                                                                 0x1
-#define SMBUS_UDID_CNTL2__SMBUS_VERSION__SHIFT                                                                0x4
-#define SMBUS_UDID_CNTL2__OEM__SHIFT                                                                          0x8
-#define SMBUS_UDID_CNTL2__ASF__SHIFT                                                                          0x9
-#define SMBUS_UDID_CNTL2__IPMI__SHIFT                                                                         0xa
-#define SMBUS_UDID_CNTL2__PEC_SUPPORTED_MASK                                                                  0x00000001L
-#define SMBUS_UDID_CNTL2__UDID_VERSION_MASK                                                                   0x0000000EL
-#define SMBUS_UDID_CNTL2__SMBUS_VERSION_MASK                                                                  0x000000F0L
-#define SMBUS_UDID_CNTL2__OEM_MASK                                                                            0x00000100L
-#define SMBUS_UDID_CNTL2__ASF_MASK                                                                            0x00000200L
-#define SMBUS_UDID_CNTL2__IPMI_MASK                                                                           0x00000400L
-//SMBUS_BACO_DUMMY
-#define SMBUS_BACO_DUMMY__BACO_DUMMY_DATA__SHIFT                                                              0x0
-#define SMBUS_BACO_DUMMY__BACO_DUMMY_DATA_MASK                                                                0xFFFFFFFFL
-//SMBUS_BACO_ADDR_RANGE0_LOW
-#define SMBUS_BACO_ADDR_RANGE0_LOW__BACO_ADDR_RANGE0_LOW__SHIFT                                               0x0
-#define SMBUS_BACO_ADDR_RANGE0_LOW__BACO_ADDR_RANGE0_LOW_MASK                                                 0x000FFFFFL
-//SMBUS_BACO_ADDR_RANGE0_HIGH
-#define SMBUS_BACO_ADDR_RANGE0_HIGH__BACO_ADDR_RANGE0_HIGH__SHIFT                                             0x0
-#define SMBUS_BACO_ADDR_RANGE0_HIGH__BACO_ADDR_RANGE0_HIGH_MASK                                               0x000FFFFFL
-//SMBUS_BACO_ADDR_RANGE1_LOW
-#define SMBUS_BACO_ADDR_RANGE1_LOW__BACO_ADDR_RANGE1_LOW__SHIFT                                               0x0
-#define SMBUS_BACO_ADDR_RANGE1_LOW__BACO_ADDR_RANGE1_LOW_MASK                                                 0x000FFFFFL
-//SMBUS_BACO_ADDR_RANGE1_HIGH
-#define SMBUS_BACO_ADDR_RANGE1_HIGH__BACO_ADDR_RANGE1_HIGH__SHIFT                                             0x0
-#define SMBUS_BACO_ADDR_RANGE1_HIGH__BACO_ADDR_RANGE1_HIGH_MASK                                               0x000FFFFFL
-//SMBUS_BACO_ADDR_RANGE2_LOW
-#define SMBUS_BACO_ADDR_RANGE2_LOW__BACO_ADDR_RANGE2_LOW__SHIFT                                               0x0
-#define SMBUS_BACO_ADDR_RANGE2_LOW__BACO_ADDR_RANGE2_LOW_MASK                                                 0x000FFFFFL
-//SMBUS_BACO_ADDR_RANGE2_HIGH
-#define SMBUS_BACO_ADDR_RANGE2_HIGH__BACO_ADDR_RANGE2_HIGH__SHIFT                                             0x0
-#define SMBUS_BACO_ADDR_RANGE2_HIGH__BACO_ADDR_RANGE2_HIGH_MASK                                               0x000FFFFFL
-//SMBUS_BACO_ADDR_RANGE3_LOW
-#define SMBUS_BACO_ADDR_RANGE3_LOW__BACO_ADDR_RANGE3_LOW__SHIFT                                               0x0
-#define SMBUS_BACO_ADDR_RANGE3_LOW__BACO_ADDR_RANGE3_LOW_MASK                                                 0x000FFFFFL
-//SMBUS_BACO_ADDR_RANGE3_HIGH
-#define SMBUS_BACO_ADDR_RANGE3_HIGH__BACO_ADDR_RANGE3_HIGH__SHIFT                                             0x0
-#define SMBUS_BACO_ADDR_RANGE3_HIGH__BACO_ADDR_RANGE3_HIGH_MASK                                               0x000FFFFFL
-//SMBUS_BACO_ADDR_RANGE4_LOW
-#define SMBUS_BACO_ADDR_RANGE4_LOW__BACO_ADDR_RANGE4_LOW__SHIFT                                               0x0
-#define SMBUS_BACO_ADDR_RANGE4_LOW__BACO_ADDR_RANGE4_LOW_MASK                                                 0x000FFFFFL
-//SMBUS_BACO_ADDR_RANGE4_HIGH
-#define SMBUS_BACO_ADDR_RANGE4_HIGH__BACO_ADDR_RANGE4_HIGH__SHIFT                                             0x0
-#define SMBUS_BACO_ADDR_RANGE4_HIGH__BACO_ADDR_RANGE4_HIGH_MASK                                               0x000FFFFFL
-//THM_GPIO_MACO_EN_CTRL
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL__SHIFT                                                        0x0
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PD__SHIFT                                                              0x1
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PU__SHIFT                                                              0x2
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN__SHIFT                                                          0x3
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S0__SHIFT                                                              0x4
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S1__SHIFT                                                              0x5
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN__SHIFT                                                            0x6
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0__SHIFT                                                          0x7
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1__SHIFT                                                          0x8
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE__SHIFT                                                     0x10
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE__SHIFT                                                              0x11
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE__SHIFT                                                      0x12
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A__SHIFT                                                               0x13
-#define THM_GPIO_MACO_EN_CTRL__Y__SHIFT                                                                       0x1f
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL_MASK                                                          0x00000001L
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PD_MASK                                                                0x00000002L
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PU_MASK                                                                0x00000004L
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN_MASK                                                            0x00000008L
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S0_MASK                                                                0x00000010L
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S1_MASK                                                                0x00000020L
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN_MASK                                                              0x00000040L
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0_MASK                                                            0x00000080L
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1_MASK                                                            0x00000100L
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE_MASK                                                       0x00010000L
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_MASK                                                                0x00020000L
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE_MASK                                                        0x00040000L
-#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_MASK                                                                 0x00080000L
-#define THM_GPIO_MACO_EN_CTRL__Y_MASK                                                                         0x80000000L
-//THM_BACO_TIMING2
-#define THM_BACO_TIMING2__BACO_AEB_ISO_EXIT_CNT__SHIFT                                                        0x0
-#define THM_BACO_TIMING2__BACO_ANA_ISO_EXIT_CNT__SHIFT                                                        0x8
-#define THM_BACO_TIMING2__BACO_EXIT_CNT__SHIFT                                                                0x10
-#define THM_BACO_TIMING2__BACO_AEB_ISO_EXIT_CNT_MASK                                                          0x000000FFL
-#define THM_BACO_TIMING2__BACO_ANA_ISO_EXIT_CNT_MASK                                                          0x0000FF00L
-#define THM_BACO_TIMING2__BACO_EXIT_CNT_MASK                                                                  0x00FF0000L
-//THM_BACO_TIMING
-#define THM_BACO_TIMING__BACO_RESET_DELAY__SHIFT                                                              0x0
-#define THM_BACO_TIMING__BACO_RESET_DELAY_MASK                                                                0x0000FFFFL
-//THM_TMON0_REMOTE_START
-#define THM_TMON0_REMOTE_START__DATA__SHIFT                                                                   0x0
-#define THM_TMON0_REMOTE_START__DATA_MASK                                                                     0xFFFFFFFFL
-//THM_TMON0_REMOTE_END
-#define THM_TMON0_REMOTE_END__DATA__SHIFT                                                                     0x0
-#define THM_TMON0_REMOTE_END__DATA_MASK                                                                       0xFFFFFFFFL
-//THM_TMON1_REMOTE_START
-#define THM_TMON1_REMOTE_START__DATA__SHIFT                                                                   0x0
-#define THM_TMON1_REMOTE_START__DATA_MASK                                                                     0xFFFFFFFFL
-//THM_TMON1_REMOTE_END
-#define THM_TMON1_REMOTE_END__DATA__SHIFT                                                                     0x0
-#define THM_TMON1_REMOTE_END__DATA_MASK                                                                       0xFFFFFFFFL
-//THM_TMON2_REMOTE_START
-#define THM_TMON2_REMOTE_START__DATA__SHIFT                                                                   0x0
-#define THM_TMON2_REMOTE_START__DATA_MASK                                                                     0xFFFFFFFFL
-//THM_TMON2_REMOTE_END
-#define THM_TMON2_REMOTE_END__DATA__SHIFT                                                                     0x0
-#define THM_TMON2_REMOTE_END__DATA_MASK                                                                       0xFFFFFFFFL
-//THM_TMON3_REMOTE_START
-#define THM_TMON3_REMOTE_START__DATA__SHIFT                                                                   0x0
-#define THM_TMON3_REMOTE_START__DATA_MASK                                                                     0xFFFFFFFFL
-//THM_TMON3_REMOTE_END
-#define THM_TMON3_REMOTE_END__DATA__SHIFT                                                                     0x0
-#define THM_TMON3_REMOTE_END__DATA_MASK                                                                       0xFFFFFFFFL
-
-#endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h
index 2573f95..e316cd7 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h
@@ -24,9 +24,9 @@
 #ifndef VEGA10_INC_H
 #define VEGA10_INC_H
 
-#include "asic_reg/vega10/THM/thm_9_0_default.h"
-#include "asic_reg/vega10/THM/thm_9_0_offset.h"
-#include "asic_reg/vega10/THM/thm_9_0_sh_mask.h"
+#include "asic_reg/thm/thm_9_0_default.h"
+#include "asic_reg/thm/thm_9_0_offset.h"
+#include "asic_reg/thm/thm_9_0_sh_mask.h"
 
 #include "asic_reg/mp/mp_9_0_offset.h"
 #include "asic_reg/mp/mp_9_0_sh_mask.h"
-- 
2.7.4