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From 6aff40ef0dae4c258cf5db4d44ec66e287b28432 Mon Sep 17 00:00:00 2001
From: "Le.Ma" <Le.Ma@amd.com>
Date: Mon, 11 Sep 2017 15:21:55 +0800
Subject: [PATCH 1781/4131] Revert "drm/amd/display: move regamma from opp to
dpp for dce"
This reverts commit d285a70ea79059941692f9dc1a5225fa2f599a82.
Revert this patch because this patch will cause error like below on some ASICs:
"[drm:dce110_opp_power_on_regamma_lut [amdgpu]] *ERROR* invalid register read; address = 0"
Will re-port it when fix is ready by DAL team.
Conflicts:
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
Change-Id: Icd9bb67423ae7b8a0607af2e53244d3e61a04109
Signed-off-by: Le.Ma <Le.Ma@amd.com>
---
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 35 ++++------------------
1 file changed, 5 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index a0e0b6d..e590f9d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2618,19 +2618,16 @@ static void dce110_apply_ctx_for_surface(
int num_planes,
struct validate_context *context)
{
- int i;
+ int i, be_idx;
if (num_planes == 0)
return;
+ be_idx = -1;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
- struct pipe_ctx *old_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i];
-
- if (stream == pipe_ctx->stream) {
- if (!pipe_ctx->top_pipe &&
- (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
- dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
+ if (stream == context->res_ctx.pipe_ctx[i].stream) {
+ be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst;
+ break;
}
}
@@ -2640,32 +2637,10 @@ static void dce110_apply_ctx_for_surface(
if (pipe_ctx->stream != stream)
continue;
- /* Need to allocate mem before program front end for Fiji */
- if (pipe_ctx->plane_res.mi != NULL)
- pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
- pipe_ctx->plane_res.mi,
- pipe_ctx->stream->timing.h_total,
- pipe_ctx->stream->timing.v_total,
- pipe_ctx->stream->timing.pix_clk_khz,
- context->stream_count);
-
dce110_program_front_end_for_pipe(dc, pipe_ctx);
-
- dc->hwss.update_plane_addr(dc, pipe_ctx);
-
program_surface_visibility(dc, pipe_ctx);
}
-
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
- struct pipe_ctx *old_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i];
-
- if ((stream == pipe_ctx->stream) &&
- (!pipe_ctx->top_pipe) &&
- (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
- dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
- }
}
static void dce110_power_down_fe(struct core_dc *dc, int fe_idx)
--
2.7.4
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