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From 284f73a432f40e6df3eb255e96a89a6fefabc4fd Mon Sep 17 00:00:00 2001
From: Yongqiang Sun <yongqiang.sun@amd.com>
Date: Fri, 28 Jul 2017 15:33:38 -0400
Subject: [PATCH 0702/4131] drm/amd/display: Keep blank until set visibility to
true after mode switch
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 21 +++++++++------------
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 4 ++++
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 83b8b19..ba80933 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1609,12 +1609,10 @@ void dc_update_surfaces_and_stream(struct dc *dc,
if (!pipe_ctx->surface || pipe_ctx->top_pipe)
continue;
- if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
- core_dc->hwss.pipe_control_lock(
- core_dc,
- pipe_ctx,
- true);
- }
+ core_dc->hwss.pipe_control_lock(
+ core_dc,
+ pipe_ctx,
+ true);
}
if (update_type == UPDATE_TYPE_FULL)
break;
@@ -1697,12 +1695,11 @@ void dc_update_surfaces_and_stream(struct dc *dc,
if (!pipe_ctx->surface || pipe_ctx->top_pipe)
continue;
- if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
- core_dc->hwss.pipe_control_lock(
- core_dc,
- pipe_ctx,
- false);
- }
+ core_dc->hwss.pipe_control_lock(
+ core_dc,
+ pipe_ctx,
+ false);
+
break;
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
index a8c254f..c46b3e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
@@ -52,6 +52,10 @@ void dce_pipe_control_lock(struct core_dc *dc,
uint32_t dcp_grph, scl, blnd, update_lock_mode, val;
struct dce_hwseq *hws = dc->hwseq;
+ /* Not lock pipe when blank */
+ if (lock && pipe->tg->funcs->is_blanked(pipe->tg))
+ return;
+
val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->pipe_idx],
BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,
BLND_SCL_V_UPDATE_LOCK, &scl,
--
2.7.4
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