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From 0073a3d9185c4ce3d4f6592767e7895b07ddefde Mon Sep 17 00:00:00 2001
From: Tony Cheng <tony.cheng@amd.com>
Date: Wed, 12 Jul 2017 09:00:14 -0400
Subject: [PATCH 0614/4131] drm/amd/display: ensure OTG is locked before
proceeding
also remove tg lock at init_hw as not all OTG is running
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 --
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 4 ++++
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h | 2 ++
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 18686be..82a96de 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -283,13 +283,11 @@ static void init_hw(struct core_dc *dc)
dc->res_pool->mpcc[i];
struct mpcc_cfg mpcc_cfg;
- tg->funcs->lock(tg);
mpcc_cfg.opp_id = 0xf;
mpcc_cfg.top_dpp_id = 0xf;
mpcc_cfg.bot_mpcc_id = 0xf;
mpcc_cfg.top_of_tree = true;
mpcc->funcs->set(mpcc, &mpcc_cfg);
- tg->funcs->unlock(tg);
tg->funcs->disable_vga(tg);
/* Blank controller using driver code instead of
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index e1899f5..12d7f35 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -573,6 +573,10 @@ static void tgn10_lock(struct timing_generator *tg)
OTG_MASTER_UPDATE_LOCK_SEL, tg->inst);
REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
OTG_MASTER_UPDATE_LOCK, 1);
+
+ REG_WAIT(OTG_MASTER_UPDATE_LOCK,
+ UPDATE_LOCK_STATUS, 1,
+ 1, 100);
}
static void tgn10_unlock(struct timing_generator *tg)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
index e287b2b..747e821 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
@@ -140,6 +140,7 @@ struct dcn_tg_registers {
SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
+ SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\
@@ -233,6 +234,7 @@ struct dcn_tg_registers {
type OTG_BLANK_DE_MODE;\
type OTG_CURRENT_BLANK_STATE;\
type OTG_MASTER_UPDATE_LOCK;\
+ type UPDATE_LOCK_STATUS;\
type OTG_UPDATE_PENDING;\
type OTG_MASTER_UPDATE_LOCK_SEL;\
type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\
--
2.7.4
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