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From 61bc660cd977cab0f44206984929c6e39a9f84d5 Mon Sep 17 00:00:00 2001
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Date: Fri, 20 Jan 2017 17:14:23 -0500
Subject: [PATCH 0180/4131] drm/amd/display: fix timing trace debug print
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +++-
drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 18 ++++++++++++------
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c627b90..c863bff 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1563,9 +1563,11 @@ void dc_update_surfaces_for_stream(struct dc *dc,
if (update_type == UPDATE_TYPE_FULL) {
/* only apply for top pipe */
- if (!pipe_ctx->top_pipe)
+ if (!pipe_ctx->top_pipe) {
core_dc->hwss.apply_ctx_for_surface(core_dc,
surface, context);
+ context_timing_trace(dc, &context->res_ctx);
+ }
} else if (updates[i].flip_addr)
core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 959c3f3..85ddf5f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -279,20 +279,26 @@ void context_timing_trace(
int i;
struct core_dc *core_dc = DC_TO_CORE(dc);
struct dal_logger *logger = core_dc->ctx->logger;
+ int h_pos[MAX_PIPES], v_pos[MAX_PIPES];
for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
- int h_pos = 0;
- int v_pos = 0;
if (pipe_ctx->stream == NULL)
continue;
- pipe_ctx->tg->funcs->get_position(pipe_ctx->tg, &h_pos, &v_pos);
- TIMING_TRACE("Pipe_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n",
- pipe_ctx->pipe_idx,
+ pipe_ctx->tg->funcs->get_position(pipe_ctx->tg, &h_pos[i], &v_pos[i]);
+ }
+ for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
+
+ if (pipe_ctx->stream == NULL)
+ continue;
+
+ TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n",
+ pipe_ctx->tg->inst,
pipe_ctx->stream->public.timing.h_total,
pipe_ctx->stream->public.timing.v_total,
- h_pos, v_pos);
+ h_pos[i], v_pos[i]);
}
}
--
2.7.4
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