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From b404ed21e078b8c38cae208e2af202d2aa2fef4f Mon Sep 17 00:00:00 2001
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Date: Tue, 20 Jun 2017 17:24:23 -0400
Subject: [PATCH 0535/4131] drm/amd/display: use different sr latencies for
dpm0 dcn bw calc
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 0aa6662..9cb0836 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -906,6 +906,16 @@ bool dcn_validate_bandwidth(
scaler_settings_calculation(v);
mode_support_and_system_configuration(v);
+ if (v->voltage_level == 0) {
+ struct core_dc *dc_core = DC_TO_CORE(&dc->public);
+
+ v->sr_enter_plus_exit_time = 9.466f;
+ v->sr_exit_time = 7.849f;
+ dc_core->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
+ dc_core->dml.soc.sr_exit_time_us = v->sr_exit_time;
+ mode_support_and_system_configuration(v);
+ }
+
if (v->voltage_level != 5) {
float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
@@ -1013,6 +1023,14 @@ bool dcn_validate_bandwidth(
&dc->dml, context, pool);
}
+ if (v->voltage_level == 0) {
+ struct core_dc *dc_core = DC_TO_CORE(&dc->public);
+
+ dc_core->dml.soc.sr_enter_plus_exit_time_us =
+ dc_core->dcn_soc.sr_enter_plus_exit_time;
+ dc_core->dml.soc.sr_exit_time_us = dc_core->dcn_soc.sr_exit_time;
+ }
+
kernel_fpu_end();
return v->voltage_level != 5;
}
--
2.7.4
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