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From c88fd429e7e4abccc1c22d42d997edeb92e31c1b Mon Sep 17 00:00:00 2001
From: Yongqiang Sun <yongqiang.sun@amd.com>
Date: Tue, 15 Dec 2015 13:59:37 -0500
Subject: [PATCH 0956/1050] drm/amd/dal: adjust DVI signal type based on pixel
clk
In case of asic supporting dual link DVI, sigal type should
be adjusted based on mode timing pixel clock, otherwise timing
on panel may be wrong.
Solution:
In case of DVI, Check mode timing pixel clock before assign
signal type from dc_sink to stream.
If pixel clock more than 165Mhz, consider it as dual link,
otherwise, single link.
Change-Id: I506931b9fe72713fbb32d08f00fbab4b6cf47760
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland<harry.wentland@amd.com>
---
.../drm/amd/dal/dc/dce_base/dce_base_resource.c | 27 ++++++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
index ba74ff5..8996475 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
@@ -33,6 +33,9 @@
#include "resource.h"
+/* Maximum TMDS single link pixel clock 165MHz */
+#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
+
static void attach_stream_to_controller(
struct resource_context *res_ctx,
struct core_stream *stream)
@@ -142,6 +145,26 @@ static bool check_timing_change(struct core_stream *cur_stream,
&new_stream->public.timing);
}
+static void set_stream_signal(struct core_stream *stream)
+{
+ struct dc_sink *dc_sink = (struct dc_sink *)stream->public.sink;
+
+ /* For asic supports dual link DVI, we should adjust signal type
+ * based on timing pixel clock. If pixel clock more than 165Mhz,
+ * signal is dual link, otherwise, single link.
+ */
+ if (dc_sink->sink_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
+ dc_sink->sink_signal == SIGNAL_TYPE_DVI_DUAL_LINK) {
+ if (stream->public.timing.pix_clk_khz >
+ TMDS_MAX_PIXEL_CLOCK_IN_KHZ)
+ dc_sink->sink_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
+ else
+ dc_sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
+ }
+
+ stream->signal = dc_sink->sink_signal;
+}
+
enum dc_status dce_base_map_resources(
const struct dc *dc,
struct validate_context *context)
@@ -207,8 +230,8 @@ enum dc_status dce_base_map_resources(
set_stream_engine_in_use(
&context->res_ctx,
stream->stream_enc);
- stream->signal =
- stream->sink->public.sink_signal;
+
+ set_stream_signal(stream);
/* TODO: Add check if ASIC support and EDID audio */
if (!stream->sink->converter_disable_audio &&
--
1.9.1
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