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From 743015c813e793b24c7607975ec2b31d68e68efd Mon Sep 17 00:00:00 2001
From: David Rokhvarg <David.Rokhvarg@amd.com>
Date: Fri, 29 Jan 2016 16:52:32 -0500
Subject: [PATCH 0758/1110] drm/amd/dal: Prevent access to PTE registers for
FPGA/Diag environment.
This fixes a regression caused by recent refactoring.
Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 89d5c65..71fa7b1 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -433,6 +433,9 @@ static bool dce110_enable_display_power_gating(
enum bp_result bp_result = BP_RESULT_OK;
enum bp_pipe_control_action cntl;
+ if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
+ return true;
+
if (power_gating == PIPE_GATING_CONTROL_INIT)
cntl = ASIC_PIPE_INIT;
else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
@@ -755,10 +758,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
bool timing_changed = context->res_ctx.controller_ctx[controller_idx]
.flags.timing_changed;
enum color_space color_space;
- struct dc_bios *dcb;
-
- dcb = dal_adapter_service_get_bios_parser(
- context->res_ctx.pool.adapter_srv);
if (timing_changed) {
/* Must blank CRTC after disabling power gating and before any
--
2.7.4
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