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From 9269a606866012c472e6dc614fd7b7c0eaa647a2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
Date: Fri, 22 May 2015 10:55:47 +0200
Subject: [PATCH 0224/1050] drm/amdgpu: drop AMDGPU_FENCE_SIGNALED_SEQ
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
It's causing issues with VMID handling and comparing the
fence value two times actually doesn't make handling faster.
Port of radeon commit "d6d5c5b8364bcc4d52cddc68bcb0a330d2af20f3".
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 12 ------------
2 files changed, 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 52d6845..411cfb9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -84,9 +84,6 @@ extern int amdgpu_vm_block_size;
#define AMDGPUFB_CONN_LIMIT 4
#define AMDGPU_BIOS_NUM_SCRATCH 8
-/* fence seq are set to this number when signaled */
-#define AMDGPU_FENCE_SIGNALED_SEQ 0LL
-
/* max number of rings */
#define AMDGPU_MAX_RINGS 16
#define AMDGPU_MAX_GFX_RINGS 1
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index be4d535..9ce6023 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -463,11 +463,7 @@ bool amdgpu_fence_signaled(struct amdgpu_fence *fence)
if (!fence)
return true;
- if (fence->seq == AMDGPU_FENCE_SIGNALED_SEQ)
- return true;
-
if (amdgpu_fence_seq_signaled(fence->ring, fence->seq)) {
- fence->seq = AMDGPU_FENCE_SIGNALED_SEQ;
if (!fence_signal(&fence->base))
FENCE_TRACE(&fence->base, "signaled from amdgpu_fence_signaled\n");
return true;
@@ -637,15 +633,11 @@ int amdgpu_fence_wait(struct amdgpu_fence *fence, bool intr)
long r;
seq[fence->ring->idx] = fence->seq;
- if (seq[fence->ring->idx] == AMDGPU_FENCE_SIGNALED_SEQ)
- return 0;
-
r = amdgpu_fence_wait_seq_timeout(fence->ring->adev, seq, intr, MAX_SCHEDULE_TIMEOUT);
if (r < 0) {
return r;
}
- fence->seq = AMDGPU_FENCE_SIGNALED_SEQ;
r = fence_signal(&fence->base);
if (!r)
FENCE_TRACE(&fence->base, "signaled from fence_wait\n");
@@ -682,10 +674,6 @@ int amdgpu_fence_wait_any(struct amdgpu_device *adev,
seq[i] = fences[i]->seq;
++num_rings;
-
- /* test if something was allready signaled */
- if (seq[i] == AMDGPU_FENCE_SIGNALED_SEQ)
- return 0;
}
/* nothing to wait for ? */
--
1.9.1
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