diff options
Diffstat (limited to 'meta-v1000/recipes-graphics')
50 files changed, 530 insertions, 3705 deletions
diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0001-amdgpu-Implement-SVM-v3.patch b/meta-v1000/recipes-graphics/drm/libdrm/0001-amdgpu-Implement-SVM-v3.patch index 8fa6e851..a8f55071 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0001-amdgpu-Implement-SVM-v3.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0001-amdgpu-Implement-SVM-v3.patch @@ -33,17 +33,18 @@ Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- - amdgpu/amdgpu.h | 50 +++++++++++++++- + amdgpu/amdgpu.h | 50 ++++++++++++++- amdgpu/amdgpu_internal.h | 3 + - amdgpu/amdgpu_vamgr.c | 145 ++++++++++++++++++++++++++++++++++++++++++++++- - 3 files changed, 193 insertions(+), 5 deletions(-) + amdgpu/amdgpu_vamgr.c | 179 ++++++++++++++++++++++++++++++++++++++++++++++++------ + 3 files changed, 212 insertions(+), 20 deletions(-) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 238b1aa..f63abdc 100644 +index 36f9105..e4f73c9 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -91,7 +91,9 @@ enum amdgpu_bo_handle_type { +@@ -91,7 +91,10 @@ enum amdgpu_bo_handle_type { enum amdgpu_gpu_va_range { /** Allocate from "normal"/general range */ @@ -51,18 +52,11 @@ index 238b1aa..f63abdc 100644 + amdgpu_gpu_va_range_general = 0, + /** Allocate from svm range */ + amdgpu_gpu_va_range_svm = 1 ++ }; - /*--------------------------------------------------------------------------*/ -@@ -1249,7 +1251,6 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo, - * <0 - Negative POSIX Error code - * - */ -- - int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, - amdgpu_bo_handle bo, - uint64_t offset, -@@ -1259,6 +1260,51 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, + enum amdgpu_sw_info { +@@ -1294,6 +1297,51 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, uint32_t ops); /** @@ -115,78 +109,110 @@ index 238b1aa..f63abdc 100644 * * \param sem - \c [out] semaphore handle diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index e68246b..3577f64 100644 +index 99b8ce0..13a7359 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h -@@ -55,6 +55,7 @@ struct amdgpu_bo_va_hole { +@@ -49,6 +49,7 @@ struct amdgpu_bo_va_hole { + }; + struct amdgpu_bo_va_mgr { - /* the start virtual address */ - uint64_t va_offset; + uint64_t va_min; uint64_t va_max; struct list_head va_holes; pthread_mutex_t bo_va_mutex; -@@ -96,6 +97,8 @@ struct amdgpu_device { - struct amdgpu_bo_va_mgr vamgr; - /** The VA manager for the 32bit address space */ - struct amdgpu_bo_va_mgr vamgr_32; +@@ -87,6 +88,8 @@ struct amdgpu_device { + struct amdgpu_bo_va_mgr vamgr_high; + /** The VA manager for the 32bit high address space */ + struct amdgpu_bo_va_mgr vamgr_high_32; + /** The VA manager for SVM address space */ + struct amdgpu_bo_va_mgr *vamgr_svm; }; struct amdgpu_bo { diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 2b1388e..2a9f28a 100644 +index 1de9f95..95483cb 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c -@@ -36,18 +36,30 @@ - int amdgpu_va_range_query(amdgpu_device_handle dev, - enum amdgpu_gpu_va_range type, uint64_t *start, uint64_t *end) +@@ -33,12 +33,23 @@ int amdgpu_va_range_query(amdgpu_device_handle dev, + enum amdgpu_gpu_va_range type, + uint64_t *start, uint64_t *end) { -- if (type == amdgpu_gpu_va_range_general) { +- if (type != amdgpu_gpu_va_range_general) +- return -EINVAL; +- +- *start = dev->dev_info.virtual_address_offset; +- *end = dev->dev_info.virtual_address_max; +- return 0; + switch (type) { -+ case amdgpu_gpu_va_range_general: - *start = dev->dev_info.virtual_address_offset; - *end = dev->dev_info.virtual_address_max; - return 0; -+ case amdgpu_gpu_va_range_svm: -+ if (dev->vamgr_svm) { -+ *start = dev->vamgr_svm->va_min; -+ *end = dev->vamgr_svm->va_max; -+ } else { -+ *start = 0ULL; -+ *end = 0ULL; -+ } -+ return 0; -+ default: -+ return -EINVAL; - } -- return -EINVAL; ++ case amdgpu_gpu_va_range_general: ++ *start = dev->dev_info.virtual_address_offset; ++ *end = dev->dev_info.virtual_address_max; ++ return 0; ++ case amdgpu_gpu_va_range_svm: ++ if (dev->vamgr_svm) { ++ *start = dev->vamgr_svm->va_min; ++ *end = dev->vamgr_svm->va_max; ++ } else { ++ *start = 0ULL; ++ *end = 0ULL; ++ } ++ return 0; ++ default: ++ return -EINVAL; ++ } } drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, - uint64_t max, uint64_t alignment) - { - mgr->va_offset = start; -+ mgr->va_min = start; +@@ -47,6 +58,7 @@ drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, + struct amdgpu_bo_va_hole *n; + mgr->va_max = max; ++ mgr->va_min = start; mgr->va_alignment = alignment; -@@ -235,7 +247,12 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, + list_inithead(&mgr->va_holes); +@@ -197,20 +209,27 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, { struct amdgpu_bo_va_mgr *vamgr; -- if (flags & AMDGPU_VA_RANGE_32_BIT) +- /* Clear the flag when the high VA manager is not initialized */ +- if (flags & AMDGPU_VA_RANGE_HIGH && !dev->vamgr_high_32.va_max) +- flags &= ~AMDGPU_VA_RANGE_HIGH; + if (amdgpu_gpu_va_range_svm == va_range_type) { + vamgr = dev->vamgr_svm; + if (!vamgr) + return -EINVAL; + } -+ else if (flags & AMDGPU_VA_RANGE_32_BIT) - vamgr = &dev->vamgr_32; - else - vamgr = &dev->vamgr; -@@ -285,3 +302,125 @@ int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) ++ else { ++ /* Clear the flag when the high VA manager is not initialized */ ++ if (flags & AMDGPU_VA_RANGE_HIGH && !dev->vamgr_high_32.va_max) ++ flags &= ~AMDGPU_VA_RANGE_HIGH; + +- if (flags & AMDGPU_VA_RANGE_HIGH) { +- if (flags & AMDGPU_VA_RANGE_32_BIT) +- vamgr = &dev->vamgr_high_32; +- else +- vamgr = &dev->vamgr_high; +- } else { +- if (flags & AMDGPU_VA_RANGE_32_BIT) +- vamgr = &dev->vamgr_32; +- else +- vamgr = &dev->vamgr; ++ if (flags & AMDGPU_VA_RANGE_HIGH) { ++ if (flags & AMDGPU_VA_RANGE_32_BIT) ++ vamgr = &dev->vamgr_high_32; ++ else ++ vamgr = &dev->vamgr_high; ++ } else { ++ if (flags & AMDGPU_VA_RANGE_32_BIT) ++ vamgr = &dev->vamgr_32; ++ else ++ vamgr = &dev->vamgr; ++ } + } + + va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment); +@@ -261,3 +280,125 @@ int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) free(va_range_handle); return 0; } @@ -314,4 +340,3 @@ index 2b1388e..2a9f28a 100644 +} -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0002-amdgpu-SVM-test-v3.patch b/meta-v1000/recipes-graphics/drm/libdrm/0002-amdgpu-SVM-test-v3.patch index 8f8c92d8..5b541e96 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0002-amdgpu-SVM-test-v3.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0002-amdgpu-SVM-test-v3.patch @@ -26,26 +26,27 @@ Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- - tests/amdgpu/basic_tests.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ + tests/amdgpu/basic_tests.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 8d5844b..b10aeb0 100644 +index 1adbddd..0a3a89d 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c -@@ -49,6 +49,7 @@ static void amdgpu_command_submission_multi_fence(void); - static void amdgpu_command_submission_sdma(void); - static void amdgpu_userptr_test(void); +@@ -48,6 +48,7 @@ static void amdgpu_userptr_test(void); static void amdgpu_semaphore_test(void); + static void amdgpu_sync_dependency_test(void); + static void amdgpu_bo_eviction_test(void); +static void amdgpu_svm_test(void); static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); -@@ -63,9 +64,11 @@ CU_TestInfo basic_tests[] = { - { "Command submission Test (Multi-Fence)", amdgpu_command_submission_multi_fence }, +@@ -69,9 +70,11 @@ CU_TestInfo basic_tests[] = { { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, { "SW semaphore Test", amdgpu_semaphore_test }, + { "Sync dependency Test", amdgpu_sync_dependency_test }, + { "SVM Test", amdgpu_svm_test }, CU_TEST_INFO_NULL, }; @@ -54,9 +55,9 @@ index 8d5844b..b10aeb0 100644 #define SDMA_PKT_HEADER_op_offset 0 #define SDMA_PKT_HEADER_op_mask 0x000000FF #define SDMA_PKT_HEADER_op_shift 0 -@@ -1329,3 +1332,54 @@ static void amdgpu_userptr_test(void) - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); +@@ -1822,3 +1825,54 @@ static void amdgpu_sync_dependency_test(void) + + free(ibs_request.dependencies); } + +static void amdgpu_svm_test(void) @@ -111,4 +112,3 @@ index 8d5844b..b10aeb0 100644 +} -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0003-amdgpu-Implement-multiGPU-SVM-support-v3.patch b/meta-v1000/recipes-graphics/drm/libdrm/0003-amdgpu-Implement-multiGPU-SVM-support-v3.patch index 7768230b..d7b9fb90 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0003-amdgpu-Implement-multiGPU-SVM-support-v3.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0003-amdgpu-Implement-multiGPU-SVM-support-v3.patch @@ -37,19 +37,20 @@ Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu_device.c | 2 ++ amdgpu/amdgpu_internal.h | 8 ++++-- - amdgpu/amdgpu_vamgr.c | 75 +++++++++++++++++++++++++++++++++++------------- + amdgpu/amdgpu_vamgr.c | 75 ++++++++++++++++++++++++++++++++++++++++--------------- 3 files changed, 63 insertions(+), 22 deletions(-) diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index 9a238d9..74d6993 100644 +index d81efcf..6d5f632 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c -@@ -279,6 +279,8 @@ int amdgpu_device_initialize(int fd, - __func__, r); - } +@@ -284,6 +284,8 @@ int amdgpu_device_initialize(int fd, + + amdgpu_parse_asic_ids(dev); + dev->svm_allocated = false; + @@ -57,10 +58,10 @@ index 9a238d9..74d6993 100644 *minor_version = dev->minor_version; *device_handle = dev; diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 3577f64..3251ff0 100644 +index 13a7359..4444e00 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h -@@ -60,6 +60,10 @@ struct amdgpu_bo_va_mgr { +@@ -54,6 +54,10 @@ struct amdgpu_bo_va_mgr { struct list_head va_holes; pthread_mutex_t bo_va_mutex; uint32_t va_alignment; @@ -71,10 +72,10 @@ index 3577f64..3251ff0 100644 }; struct amdgpu_va { -@@ -97,8 +101,8 @@ struct amdgpu_device { - struct amdgpu_bo_va_mgr vamgr; - /** The VA manager for the 32bit address space */ - struct amdgpu_bo_va_mgr vamgr_32; +@@ -88,8 +92,8 @@ struct amdgpu_device { + struct amdgpu_bo_va_mgr vamgr_high; + /** The VA manager for the 32bit high address space */ + struct amdgpu_bo_va_mgr vamgr_high_32; - /** The VA manager for SVM address space */ - struct amdgpu_bo_va_mgr *vamgr_svm; + /** svm range allocated */ @@ -83,10 +84,10 @@ index 3577f64..3251ff0 100644 struct amdgpu_bo { diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 2a9f28a..54711ee 100644 +index 95483cb..4a0431b 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c -@@ -33,6 +33,9 @@ +@@ -29,6 +29,9 @@ #include "amdgpu_internal.h" #include "util_math.h" @@ -94,22 +95,22 @@ index 2a9f28a..54711ee 100644 +static struct amdgpu_bo_va_mgr vamgr_svm; + int amdgpu_va_range_query(amdgpu_device_handle dev, - enum amdgpu_gpu_va_range type, uint64_t *start, uint64_t *end) - { -@@ -42,9 +45,9 @@ int amdgpu_va_range_query(amdgpu_device_handle dev, - *end = dev->dev_info.virtual_address_max; - return 0; - case amdgpu_gpu_va_range_svm: -- if (dev->vamgr_svm) { -- *start = dev->vamgr_svm->va_min; -- *end = dev->vamgr_svm->va_max; -+ if (vamgr_svm.valid) { -+ *start = vamgr_svm.va_min; -+ *end = vamgr_svm.va_max; - } else { - *start = 0ULL; - *end = 0ULL; -@@ -248,8 +251,8 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, + enum amdgpu_gpu_va_range type, + uint64_t *start, uint64_t *end) +@@ -39,9 +42,9 @@ int amdgpu_va_range_query(amdgpu_device_handle dev, + *end = dev->dev_info.virtual_address_max; + return 0; + case amdgpu_gpu_va_range_svm: +- if (dev->vamgr_svm) { +- *start = dev->vamgr_svm->va_min; +- *end = dev->vamgr_svm->va_max; ++ if (vamgr_svm.valid) { ++ *start = vamgr_svm.va_min; ++ *end = vamgr_svm.va_max; + } else { + *start = 0ULL; + *end = 0ULL; +@@ -210,8 +213,8 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, struct amdgpu_bo_va_mgr *vamgr; if (amdgpu_gpu_va_range_svm == va_range_type) { @@ -119,8 +120,8 @@ index 2a9f28a..54711ee 100644 + if (!vamgr->valid) return -EINVAL; } - else if (flags & AMDGPU_VA_RANGE_32_BIT) -@@ -329,6 +332,27 @@ int amdgpu_svm_init(amdgpu_device_handle dev) + else { +@@ -307,6 +310,27 @@ int amdgpu_svm_init(amdgpu_device_handle dev) /* return value of this function. */ int ret; @@ -148,7 +149,7 @@ index 2a9f28a..54711ee 100644 ret = amdgpu_va_range_query(dev, amdgpu_gpu_va_range_general, &start, &end); if (ret) return ret; -@@ -356,16 +380,9 @@ int amdgpu_svm_init(amdgpu_device_handle dev) +@@ -334,16 +358,9 @@ int amdgpu_svm_init(amdgpu_device_handle dev) cpu_address = mmap((void *)start, size, PROT_NONE, MAP_PRIVATE | MAP_NORESERVE | MAP_ANONYMOUS, -1, 0); if (cpu_address == (void *)start) { @@ -163,12 +164,12 @@ index 2a9f28a..54711ee 100644 - ret = 0; - } + amdgpu_vamgr_init(&vamgr_svm, start, start + size, -+ dev->dev_info.virtual_address_alignment); ++ dev->dev_info.virtual_address_alignment); + ret = 0; break; } else if (cpu_address == MAP_FAILED) { /* Probably there is no space in this process's address space for -@@ -382,17 +399,35 @@ int amdgpu_svm_init(amdgpu_device_handle dev) +@@ -360,17 +377,35 @@ int amdgpu_svm_init(amdgpu_device_handle dev) } } @@ -188,7 +189,7 @@ index 2a9f28a..54711ee 100644 - dev->vamgr_svm->va_max - dev->vamgr_svm->va_min); - free(dev->vamgr_svm); + if (dev->svm_allocated) { -+ amdgpu_vamgr_free_va(&dev->vamgr, vamgr_svm.va_min, ++ amdgpu_vamgr_free_va(&dev->vamgr, vamgr_svm.va_min, + vamgr_svm.va_max - vamgr_svm.va_min); + dev->svm_allocated = false; + @@ -196,7 +197,7 @@ index 2a9f28a..54711ee 100644 + /* This is the last device referencing SVM. */ + amdgpu_vamgr_deinit(&vamgr_svm); + munmap((void *)vamgr_svm.va_min, -+ vamgr_svm.va_max - vamgr_svm.va_min); ++ vamgr_svm.va_max - vamgr_svm.va_min); + vamgr_svm.va_max = 0; + } } @@ -211,4 +212,3 @@ index 2a9f28a..54711ee 100644 int amdgpu_svm_commit(amdgpu_va_handle va_range_handle, -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0004-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v4.patch b/meta-v1000/recipes-graphics/drm/libdrm/0004-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v4.patch index bd48fd49..31166778 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0004-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v4.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0004-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v4.patch @@ -34,31 +34,33 @@ Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Change-Id: I481155784e7ebcfda3bfc7e68932a33d01d6843a + +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- tests/amdgpu/basic_tests.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index b10aeb0..7dfc0e2 100644 +index 0a3a89d..96e98e3 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c -@@ -50,6 +50,7 @@ static void amdgpu_command_submission_sdma(void); - static void amdgpu_userptr_test(void); - static void amdgpu_semaphore_test(void); +@@ -49,6 +49,7 @@ static void amdgpu_semaphore_test(void); + static void amdgpu_sync_dependency_test(void); + static void amdgpu_bo_eviction_test(void); static void amdgpu_svm_test(void); +static void amdgpu_multi_svm_test(void); static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); -@@ -65,6 +66,7 @@ CU_TestInfo basic_tests[] = { - { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, +@@ -71,6 +72,7 @@ CU_TestInfo basic_tests[] = { { "SW semaphore Test", amdgpu_semaphore_test }, + { "Sync dependency Test", amdgpu_sync_dependency_test }, { "SVM Test", amdgpu_svm_test }, + { "SVM Test (multi-GPUs)", amdgpu_multi_svm_test }, CU_TEST_INFO_NULL, }; #define BUFFER_SIZE (8 * 1024) -@@ -1383,3 +1385,71 @@ static void amdgpu_svm_test(void) +@@ -1876,3 +1878,71 @@ static void amdgpu_svm_test(void) amdgpu_svm_deinit(device_handle); } @@ -132,4 +134,3 @@ index b10aeb0..7dfc0e2 100644 +} -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0005-amdgpu-add-query-for-aperture-va-range.patch b/meta-v1000/recipes-graphics/drm/libdrm/0005-amdgpu-add-query-for-aperture-va-range.patch index a8a4266c..dbce268d 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0005-amdgpu-add-query-for-aperture-va-range.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0005-amdgpu-add-query-for-aperture-va-range.patch @@ -8,6 +8,7 @@ Signed-off-by: Flora Cui <flora.cui@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu.h | 30 ++++++++++++++++++++++++++++++ amdgpu/amdgpu_gpu_info.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ @@ -15,10 +16,10 @@ Signed-off-by: Avinash M N <avimn@amd.com> 3 files changed, 93 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index f63abdc..f0eecb7 100644 +index e4f73c9..d2657fe 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -1106,6 +1106,36 @@ int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, +@@ -1141,6 +1141,36 @@ int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, unsigned size, void *value); /** @@ -109,12 +110,12 @@ index 1efffc6..697360b 100644 + end); +} diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index d9aa4a3..51b1d51 100644 +index a023b47..db80956 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -612,6 +612,9 @@ struct drm_amdgpu_cs_chunk_data { - /* Number of VRAM page faults on CPU access. */ +@@ -660,6 +660,9 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E + #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F +/* virtual range */ +#define AMDGPU_INFO_VIRTUAL_RANGE 0x51 @@ -122,7 +123,7 @@ index d9aa4a3..51b1d51 100644 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 -@@ -668,6 +671,11 @@ struct drm_amdgpu_info { +@@ -716,6 +719,11 @@ struct drm_amdgpu_info { __u32 flags; } read_mmr_reg; @@ -134,7 +135,7 @@ index d9aa4a3..51b1d51 100644 struct drm_amdgpu_query_fw query_fw; struct { -@@ -872,6 +880,16 @@ struct drm_amdgpu_info_vce_clock_table { +@@ -927,6 +935,16 @@ struct drm_amdgpu_info_vce_clock_table { #define AMDGPU_FAMILY_AI 141 /* Vega10 */ #define AMDGPU_FAMILY_RV 142 /* Raven */ @@ -153,4 +154,3 @@ index d9aa4a3..51b1d51 100644 #endif -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0006-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0006-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag-v2.patch index 09f73e0a..2e38cbce 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0006-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0006-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag-v2.patch @@ -19,25 +19,25 @@ Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Flora Cui <Flora.Cui@amd.com> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- include/drm/amdgpu_drm.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 51b1d51..b3ce535 100644 +index 20de8ca..940bee8 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -88,6 +88,10 @@ extern "C" { - /* Flag that allocating the BO should use linear VRAM */ - #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) +@@ -96,6 +96,10 @@ extern "C" { + /* Flag that BO sharing will be explicitly synchronized */ + #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) +/* Hybrid specific */ +/* Flag that the memory allocation should be pinned */ -+#define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) ++#define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) + struct drm_amdgpu_gem_create_in { /** the requested memory size */ __u64 bo_size; -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0007-amdgpu-add-sparse-flag-for-bo-creatation-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0007-amdgpu-add-sparse-flag-for-bo-creatation-v2.patch index 9b4e7a0a..f9ee1531 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0007-amdgpu-add-sparse-flag-for-bo-creatation-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0007-amdgpu-add-sparse-flag-for-bo-creatation-v2.patch @@ -10,23 +10,23 @@ update GEM flag bit for 64-bit extension Change-Id: Ie291d391d0f68e7ff9028b3713808c38002d84c6 Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Flora Cui <Flora.Cui@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- include/drm/amdgpu_drm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index b3ce535..afacd62 100644 +index 940bee8..191c5c2 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -89,6 +89,8 @@ extern "C" { - #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) +@@ -97,6 +97,8 @@ extern "C" { + #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) /* Hybrid specific */ +/* Flag that the memory should be in SPARSE resource */ -+#define AMDGPU_GEM_CREATE_SPARSE (1ULL << 29) ++#define AMDGPU_GEM_CREATE_SPARSE (1ULL << 29) /* Flag that the memory allocation should be pinned */ - #define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) + #define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0008-amdgpu-add-amdgpu_query_capability-interface-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0008-amdgpu-add-amdgpu_query_capability-interface-v2.patch index c2907a39..907bbcac 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0008-amdgpu-add-amdgpu_query_capability-interface-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0008-amdgpu-add-amdgpu_query_capability-interface-v2.patch @@ -17,6 +17,7 @@ Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu.h | 20 ++++++++++++++++++++ amdgpu/amdgpu_gpu_info.c | 7 +++++++ @@ -24,7 +25,7 @@ Signed-off-by: Avinash M N <avimn@amd.com> 3 files changed, 39 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index f0eecb7..7669530 100644 +index d2657fe..10f458a 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -42,6 +42,7 @@ extern "C" { @@ -47,7 +48,7 @@ index f0eecb7..7669530 100644 /*--------------------------------------------------------------------------*/ /* ----------------------------- Enums ------------------------------------ */ /*--------------------------------------------------------------------------*/ -@@ -1075,6 +1081,20 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, +@@ -1093,6 +1099,20 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, unsigned size, void *value); /** @@ -65,9 +66,9 @@ index f0eecb7..7669530 100644 + struct drm_amdgpu_capability *cap); + +/** - * Query information about GDS + * Query hardware or driver information. * - * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() + * The return size is query-specific and depends on the "info_id" parameter. diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c index 697360b..dddf6e7 100644 --- a/amdgpu/amdgpu_gpu_info.c @@ -87,19 +88,19 @@ index 697360b..dddf6e7 100644 int32_t *result) { diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index afacd62..e76212b 100644 +index 4465eb4..616683e 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -618,6 +618,8 @@ struct drm_amdgpu_cs_chunk_data { - /* Number of VRAM page faults on CPU access. */ +@@ -666,6 +666,8 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E + #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F +/* gpu capability */ +#define AMDGPU_INFO_CAPABILITY 0x50 /* virtual range */ #define AMDGPU_INFO_VIRTUAL_RANGE 0x51 -@@ -896,6 +898,16 @@ struct drm_amdgpu_virtual_range { +@@ -951,6 +953,16 @@ struct drm_amdgpu_virtual_range { uint64_t end; }; @@ -118,4 +119,3 @@ index afacd62..e76212b 100644 #endif -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0009-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch b/meta-v1000/recipes-graphics/drm/libdrm/0009-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch index 19c9b676..291bf640 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0009-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0009-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch @@ -1,7 +1,7 @@ -From 3d9a1994c39c51c2d4471e1ae4c93ce421f9dbab Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Thu, 26 Nov 2015 17:01:07 +0800 -Subject: [PATCH 09/39] amdgpu: add amdgpu_find_bo_by_cpu_mapping interface +From aab24091f243d7b73ad4252365d09254ad393106 Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Mon, 18 Dec 2017 15:18:51 +0500 +Subject: [PATCH] amdgpu: add amdgpu_find_bo_by_cpu_mapping interface MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -13,6 +13,7 @@ Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Awais Belal <awais_belal@mentor.com> --- amdgpu/amdgpu.h | 24 ++++++++++++++++++++++++ amdgpu/amdgpu_bo.c | 37 +++++++++++++++++++++++++++++++++++++ @@ -20,7 +21,7 @@ Signed-off-by: Avinash M N <avimn@amd.com> 3 files changed, 75 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 7669530..755d746 100644 +index 8247f82a..0a54855b 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -677,6 +677,30 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, @@ -55,10 +56,10 @@ index 7669530..755d746 100644 * * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 5ac456b..9a110a0 100644 +index 3853fd03..3a8d08af 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c -@@ -529,6 +529,43 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo, +@@ -533,6 +533,43 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo, } } @@ -103,28 +104,28 @@ index 5ac456b..9a110a0 100644 void *cpu, uint64_t size, diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index e76212b..1919c28 100644 +index 2563779c..9734e963 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -52,6 +52,8 @@ extern "C" { - #define DRM_AMDGPU_GEM_USERPTR 0x11 - #define DRM_AMDGPU_WAIT_FENCES 0x12 +@@ -54,6 +54,8 @@ extern "C" { #define DRM_AMDGPU_VM 0x13 + #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 + #define DRM_AMDGPU_SCHED 0x15 +/* hybrid specific ioctls */ +#define DRM_AMDGPU_GEM_FIND_BO 0x5f #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) -@@ -67,6 +69,8 @@ extern "C" { - #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) - #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) +@@ -71,6 +73,8 @@ extern "C" { #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) + #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) + #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) +/* hybrid specific ioctls */ +#define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 -@@ -237,6 +241,16 @@ struct drm_amdgpu_gem_userptr { +@@ -269,6 +273,16 @@ struct drm_amdgpu_gem_userptr { __u32 handle; }; @@ -142,5 +143,5 @@ index e76212b..1919c28 100644 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 -- -2.7.4 +2.11.1 diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0010-amdgpu-support-alloc-va-from-range-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0010-amdgpu-support-alloc-va-from-range-v2.patch index 84675e1f..55ebb0be 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0010-amdgpu-support-alloc-va-from-range-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0010-amdgpu-support-alloc-va-from-range-v2.patch @@ -15,16 +15,17 @@ Change-Id: I05f24e44863aeffa7bcd735bf787a5328d587044 Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: David Mao <david.mao@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- - amdgpu/amdgpu.h | 51 ++++++++++++++ - amdgpu/amdgpu_vamgr.c | 179 ++++++++++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 230 insertions(+) + amdgpu/amdgpu.h | 51 +++++++++++++++++ + amdgpu/amdgpu_vamgr.c | 152 ++++++++++++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 203 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 755d746..8bcb808 100644 +index 56a5a0d..9e3ce7f 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -1251,6 +1251,57 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, +@@ -1287,6 +1287,57 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, uint64_t flags); /** @@ -83,11 +84,11 @@ index 755d746..8bcb808 100644 * * diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 54711ee..63124a4 100644 +index 0177bfb..906303b 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c -@@ -169,6 +169,104 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, - return offset; +@@ -149,6 +149,77 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, + return AMDGPU_INVALID_VA_ADDRESS; } +static uint64_t amdgpu_vamgr_find_va_in_range(struct amdgpu_bo_va_mgr *mgr, uint64_t size, @@ -157,41 +158,14 @@ index 54711ee..63124a4 100644 + } + } + -+ if (mgr->va_offset > range_max) { -+ pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return AMDGPU_INVALID_VA_ADDRESS; -+ } else if (mgr->va_offset > range_min) { -+ offset = mgr->va_offset; -+ waste = offset % alignment; -+ waste = waste ? alignment - waste : 0; -+ if (offset + waste + size > range_max) { -+ pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return AMDGPU_INVALID_VA_ADDRESS; -+ } -+ } else { -+ offset = mgr->va_offset; -+ waste = range_min % alignment; -+ waste = waste ? alignment - waste : 0; -+ waste += range_min - offset ; -+ } -+ -+ if (waste) { -+ n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); -+ n->size = waste; -+ n->offset = offset; -+ list_add(&n->list, &mgr->va_holes); -+ } -+ -+ offset += waste; -+ mgr->va_offset = size + offset; + pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return offset; ++ return AMDGPU_INVALID_VA_ADDRESS; +} + - drm_private void + static drm_private void amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size) { -@@ -294,6 +392,87 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, +@@ -276,6 +347,87 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, return 0; } @@ -281,4 +255,3 @@ index 54711ee..63124a4 100644 if(!va_range_handle || !va_range_handle->address) -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0011-tests-amdgpu-add-alloc-va-from-range-test-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0011-tests-amdgpu-add-alloc-va-from-range-test-v2.patch index 50dfc03b..f5a477f9 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0011-tests-amdgpu-add-alloc-va-from-range-test-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0011-tests-amdgpu-add-alloc-va-from-range-test-v2.patch @@ -12,31 +12,32 @@ move va_range_test above svm_test Change-Id: Ie430345b42da6884d5296f057d4214b2d3f12788 Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- tests/amdgpu/basic_tests.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 7dfc0e2..41a702d 100644 +index 96e98e3..0d9a810 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c -@@ -51,6 +51,7 @@ static void amdgpu_userptr_test(void); - static void amdgpu_semaphore_test(void); +@@ -50,6 +50,7 @@ static void amdgpu_sync_dependency_test(void); + static void amdgpu_bo_eviction_test(void); static void amdgpu_svm_test(void); static void amdgpu_multi_svm_test(void); +static void amdgpu_va_range_test(void); static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); -@@ -65,6 +66,7 @@ CU_TestInfo basic_tests[] = { - { "Command submission Test (Multi-Fence)", amdgpu_command_submission_multi_fence }, +@@ -71,6 +72,7 @@ CU_TestInfo basic_tests[] = { { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, { "SW semaphore Test", amdgpu_semaphore_test }, + { "Sync dependency Test", amdgpu_sync_dependency_test }, + { "VA range Test", amdgpu_va_range_test}, { "SVM Test", amdgpu_svm_test }, { "SVM Test (multi-GPUs)", amdgpu_multi_svm_test }, CU_TEST_INFO_NULL, -@@ -1453,3 +1455,55 @@ static void amdgpu_multi_svm_test(void) +@@ -1946,3 +1948,55 @@ static void amdgpu_multi_svm_test(void) amdgpu_svm_deinit(device_handles[0]); } @@ -94,4 +95,3 @@ index 7dfc0e2..41a702d 100644 +} -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0016-amdgpu-Add-interface-amdgpu_get_fb_id-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0016-amdgpu-Add-interface-amdgpu_get_fb_id-v2.patch index 2b340bb3..ace4bc1f 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0016-amdgpu-Add-interface-amdgpu_get_fb_id-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0016-amdgpu-Add-interface-amdgpu_get_fb_id-v2.patch @@ -14,6 +14,7 @@ Fix memory leak in amdgpu_get_fb_id Change-Id: I336fab1585bbdcf6f789c4bab533e4d1f01842ec Signed-off-by: jqdeng <Emily.Deng@amd.com> Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu-symbol-check | 1 + amdgpu/amdgpu.h | 15 +++++++++++++ @@ -21,29 +22,29 @@ Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> 3 files changed, 68 insertions(+) diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check -index c5b85b5..f5cf9ff 100755 +index 90b7a1d..cf03353 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check -@@ -59,6 +59,7 @@ amdgpu_read_mm_registers - amdgpu_va_range_alloc - amdgpu_va_range_free +@@ -70,6 +70,7 @@ amdgpu_va_range_free amdgpu_va_range_query + amdgpu_vm_reserve_vmid + amdgpu_vm_unreserve_vmid +amdgpu_get_fb_id EOF done) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 6786007..9483080 100644 +index 1eca68f..1f1b120 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -642,6 +642,21 @@ int amdgpu_bo_import(amdgpu_device_handle dev, +@@ -647,6 +647,21 @@ int amdgpu_bo_import(amdgpu_device_handle dev, struct amdgpu_bo_import_result *output); /** + * Allow others to get access to crtc's framebuffer + * + * \param dev - \c [in] Device handle. -+ * See #amdgpu_device_initialize() ++ * See #amdgpu_device_initialize() + * \param fb_id - \c [out] the first crtc's framebuffer's buffer_id + * + * \return 0 on success\n @@ -59,10 +60,10 @@ index 6786007..9483080 100644 * * \param dev - [in] Device handle. See #amdgpu_device_initialize() diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 0760be9..aa37462 100644 +index 5ffda7e..80c4e95 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c -@@ -43,6 +43,7 @@ +@@ -39,6 +39,7 @@ #include "amdgpu_internal.h" #include "util_hash_table.h" #include "util_math.h" @@ -70,7 +71,7 @@ index 0760be9..aa37462 100644 static void amdgpu_close_kms_handle(amdgpu_device_handle dev, uint32_t handle) -@@ -417,6 +418,57 @@ int amdgpu_bo_import(amdgpu_device_handle dev, +@@ -391,6 +392,57 @@ int amdgpu_bo_import(amdgpu_device_handle dev, return 0; } @@ -127,7 +128,6 @@ index 0760be9..aa37462 100644 + int amdgpu_bo_free(amdgpu_bo_handle buf_handle) { - /* Just drop the reference. */ + struct amdgpu_device *dev; -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0017-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0017-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id-v2.patch index 8766f2de..856be722 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0017-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0017-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id-v2.patch @@ -14,6 +14,7 @@ Fix memory leak in amdgpu_get_bo_from_fb_id Change-Id: Id315a05147035b4ce16f72d627881c5166015473 Signed-off-by: jqdeng <Emily.Deng@amd.com> Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu-symbol-check | 1 + amdgpu/amdgpu.h | 17 ++++++++ @@ -21,22 +22,22 @@ Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> 3 files changed, 119 insertions(+) diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check -index f5cf9ff..82ff12c 100755 +index cf03353..a84ba7e 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check -@@ -60,6 +60,7 @@ amdgpu_va_range_alloc - amdgpu_va_range_free - amdgpu_va_range_query +@@ -71,6 +71,7 @@ amdgpu_va_range_query + amdgpu_vm_reserve_vmid + amdgpu_vm_unreserve_vmid amdgpu_get_fb_id +amdgpu_get_bo_from_fb_id EOF done) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 9483080..38b3597 100644 +index 01cad97..0ded2cb 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -657,6 +657,23 @@ int amdgpu_bo_import(amdgpu_device_handle dev, +@@ -662,6 +662,23 @@ int amdgpu_bo_import(amdgpu_device_handle dev, int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id); /** @@ -61,10 +62,10 @@ index 9483080..38b3597 100644 * * \param dev - [in] Device handle. See #amdgpu_device_initialize() diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index aa37462..fef6152 100644 +index 86d39f9..3031d37 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c -@@ -469,6 +469,107 @@ int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id) +@@ -446,6 +446,107 @@ int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id) return r; } @@ -171,7 +172,6 @@ index aa37462..fef6152 100644 + int amdgpu_bo_free(amdgpu_bo_handle buf_handle) { - /* Just drop the reference. */ + struct amdgpu_device *dev; -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0018-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch b/meta-v1000/recipes-graphics/drm/libdrm/0018-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch index 856abdf1..3cc26e32 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0018-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0018-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch @@ -12,36 +12,35 @@ stop fb_id test for ASIC without output Signed-off-by: jqdeng <Emily.Deng@amd.com> Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Flora Cui <Flora.Cui@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- - tests/amdgpu/bo_tests.c | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) + tests/amdgpu/bo_tests.c | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c -index 74b5e77..83f42a9 100644 +index 9d4da4a..2ab31c1 100644 --- a/tests/amdgpu/bo_tests.c +++ b/tests/amdgpu/bo_tests.c -@@ -46,6 +46,8 @@ static amdgpu_va_handle va_handle; - static void amdgpu_bo_export_import(void); - static void amdgpu_bo_metadata(void); +@@ -44,6 +44,7 @@ static void amdgpu_bo_metadata(void); static void amdgpu_bo_map_unmap(void); + static void amdgpu_memory_alloc(void); + static void amdgpu_mem_fail_alloc(void); +static void amdgpu_get_fb_id_and_handle(void); -+ CU_TestInfo bo_tests[] = { { "Export/Import", amdgpu_bo_export_import }, -@@ -53,6 +55,7 @@ CU_TestInfo bo_tests[] = { - { "Metadata", amdgpu_bo_metadata }, - #endif +@@ -51,6 +52,7 @@ CU_TestInfo bo_tests[] = { { "CPU map/unmap", amdgpu_bo_map_unmap }, + { "Memory alloc Test", amdgpu_memory_alloc }, + { "Memory fail alloc Test", amdgpu_mem_fail_alloc }, + { "GET FB_ID AND FB_HANDLE", amdgpu_get_fb_id_and_handle }, CU_TEST_INFO_NULL, }; -@@ -195,3 +198,22 @@ static void amdgpu_bo_map_unmap(void) - r = amdgpu_bo_cpu_unmap(buffer_handle); +@@ -194,6 +196,25 @@ static void amdgpu_bo_map_unmap(void) CU_ASSERT_EQUAL(r, 0); } -+ + +static void amdgpu_get_fb_id_and_handle(void) +{ + uint32_t *ptr; @@ -60,6 +59,9 @@ index 74b5e77..83f42a9 100644 + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_NOT_EQUAL(output.buf_handle, 0); +} ++ + static void amdgpu_memory_alloc(void) + { + amdgpu_bo_handle bo; -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0019-drm-amdgpu-add-freesync-ioctl-defines.patch b/meta-v1000/recipes-graphics/drm/libdrm/0019-drm-amdgpu-add-freesync-ioctl-defines.patch index 7ac4a6e1..9e10fea2 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0019-drm-amdgpu-add-freesync-ioctl-defines.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0019-drm-amdgpu-add-freesync-ioctl-defines.patch @@ -7,31 +7,32 @@ Change-Id: Id5d607fee4ae119015ca685a508a2ee140a8e331 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Flora Cui <Flora.Cui@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- include/drm/amdgpu_drm.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 1919c28..bd34a86 100644 +index 982dd22..0598a47 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -53,6 +53,7 @@ extern "C" { - #define DRM_AMDGPU_WAIT_FENCES 0x12 - #define DRM_AMDGPU_VM 0x13 +@@ -55,6 +55,7 @@ extern "C" { + #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 + #define DRM_AMDGPU_SCHED 0x15 /* hybrid specific ioctls */ -+#define DRM_AMDGPU_FREESYNC 0x5d ++#define DRM_AMDGPU_FREESYNC 0x5d #define DRM_AMDGPU_GEM_FIND_BO 0x5f #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) -@@ -71,6 +72,7 @@ extern "C" { - #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) +@@ -75,6 +76,7 @@ extern "C" { + #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) /* hybrid specific ioctls */ #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) -+#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) ++#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 -@@ -922,6 +924,19 @@ struct drm_amdgpu_capability { +@@ -992,6 +994,19 @@ struct drm_amdgpu_capability { uint32_t direct_gma_size; }; @@ -39,13 +40,13 @@ index 1919c28..bd34a86 100644 + * Definition of free sync enter and exit signals + * We may have more options in the future + */ -+#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1 -+#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2 ++#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1 ++#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2 + +struct drm_amdgpu_freesync { -+ __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */ -+ /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */ -+ __u32 spare[7]; ++ __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */ ++ /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */ ++ __u32 spare[7]; +}; + #if defined(__cplusplus) @@ -53,4 +54,3 @@ index 1919c28..bd34a86 100644 #endif -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0020-amdgpu-implement-direct-gma.patch b/meta-v1000/recipes-graphics/drm/libdrm/0020-amdgpu-implement-direct-gma.patch index 529fee1d..d589b7d5 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0020-amdgpu-implement-direct-gma.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0020-amdgpu-implement-direct-gma.patch @@ -6,6 +6,7 @@ Subject: [PATCH 20/39] amdgpu: implement direct gma Change-Id: I37a6a0f79a91b8e793fc90eb3955045bebf24848 Signed-off-by: Flora Cui <Flora.Cui@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu.h | 43 +++++++++++++++++++++++++++++++++++++ amdgpu/amdgpu_bo.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++- @@ -13,10 +14,10 @@ Signed-off-by: Avinash M N <avimn@amd.com> 3 files changed, 109 insertions(+), 1 deletion(-) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 38b3597..e7a566f 100644 +index f2baa26..423ad28 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -731,6 +731,49 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, +@@ -736,6 +736,49 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, amdgpu_bo_handle *buf_handle, uint64_t *offset_in_bo); @@ -47,8 +48,8 @@ index 38b3597..e7a566f 100644 + * It is responsibility of caller to correctly specify physical_address +*/ +int amdgpu_create_bo_from_phys_mem(amdgpu_device_handle dev, -+ uint64_t phys_address, uint64_t size, -+ amdgpu_bo_handle *buf_handle); ++ uint64_t phys_address, uint64_t size, ++ amdgpu_bo_handle *buf_handle); + +/** + * Get physical address from BO @@ -62,25 +63,25 @@ index 38b3597..e7a566f 100644 + * +*/ +int amdgpu_bo_get_phys_address(amdgpu_bo_handle buf_handle, -+ uint64_t *phys_address); ++ uint64_t *phys_address); /** * Free previosuly allocated memory diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index fef6152..5a9cdbe2 100644 +index 8737d51..8f32d8d 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c -@@ -87,7 +87,8 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev, +@@ -60,7 +60,8 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev, int r = 0; /* It's an error if the heap is not specified */ - if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM))) + if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM -+ | AMDGPU_GEM_DOMAIN_DGMA))) ++ | AMDGPU_GEM_DOMAIN_DGMA))) return -EINVAL; bo = calloc(1, sizeof(struct amdgpu_bo)); -@@ -570,6 +571,58 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc +@@ -544,6 +545,58 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc return r; } @@ -138,28 +139,28 @@ index fef6152..5a9cdbe2 100644 + int amdgpu_bo_free(amdgpu_bo_handle buf_handle) { - /* Just drop the reference. */ + struct amdgpu_device *dev; diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index bd34a86..b515809 100644 +index 0598a47..088cb3f 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -53,6 +53,7 @@ extern "C" { - #define DRM_AMDGPU_WAIT_FENCES 0x12 - #define DRM_AMDGPU_VM 0x13 +@@ -55,6 +55,7 @@ extern "C" { + #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 + #define DRM_AMDGPU_SCHED 0x15 /* hybrid specific ioctls */ -+#define DRM_AMDGPU_GEM_DGMA 0x5c - #define DRM_AMDGPU_FREESYNC 0x5d ++#define DRM_AMDGPU_GEM_DGMA 0x5c + #define DRM_AMDGPU_FREESYNC 0x5d #define DRM_AMDGPU_GEM_FIND_BO 0x5f -@@ -71,6 +72,7 @@ extern "C" { - #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) - #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) +@@ -75,6 +76,7 @@ extern "C" { + #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) + #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) /* hybrid specific ioctls */ -+#define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma) ++#define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma) #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) - #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) + #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) -@@ -80,6 +82,7 @@ extern "C" { +@@ -84,6 +86,7 @@ extern "C" { #define AMDGPU_GEM_DOMAIN_GDS 0x8 #define AMDGPU_GEM_DOMAIN_GWS 0x10 #define AMDGPU_GEM_DOMAIN_OA 0x20 @@ -167,17 +168,17 @@ index bd34a86..b515809 100644 /* Flag that CPU access will be required for the case of VRAM domain */ #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) -@@ -243,6 +246,15 @@ struct drm_amdgpu_gem_userptr { +@@ -283,6 +286,15 @@ struct drm_amdgpu_gem_userptr { __u32 handle; }; -+#define AMDGPU_GEM_DGMA_IMPORT 0 -+#define AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR 1 ++#define AMDGPU_GEM_DGMA_IMPORT 0 ++#define AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR 1 +struct drm_amdgpu_gem_dgma { -+ uint64_t addr; -+ uint64_t size; -+ uint32_t op; -+ uint32_t handle; ++ uint64_t addr; ++ uint64_t size; ++ uint32_t op; ++ uint32_t handle; +}; + struct drm_amdgpu_gem_find_bo { @@ -185,4 +186,3 @@ index bd34a86..b515809 100644 uint64_t size; -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0021-tests-amdgpu-add-direct-gma-test.patch b/meta-v1000/recipes-graphics/drm/libdrm/0021-tests-amdgpu-add-direct-gma-test.patch index 076e4137..cbec2bb8 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0021-tests-amdgpu-add-direct-gma-test.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0021-tests-amdgpu-add-direct-gma-test.patch @@ -5,12 +5,13 @@ Subject: [PATCH 21/39] tests/amdgpu: add direct gma test Change-Id: Ib00252eff16a84f16f01039ff39f957bff903bae Signed-off-by: Flora Cui <Flora.Cui@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- - tests/amdgpu/bo_tests.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 63 insertions(+), 1 deletion(-) + tests/amdgpu/bo_tests.c | 63 +++++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 63 insertions(+) diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c -index 83f42a9..930a073 100644 +index 2c03fd2..58a00ec 100644 --- a/tests/amdgpu/bo_tests.c +++ b/tests/amdgpu/bo_tests.c @@ -26,6 +26,7 @@ @@ -21,28 +22,26 @@ index 83f42a9..930a073 100644 #include "CUnit/Basic.h" -@@ -47,7 +48,7 @@ static void amdgpu_bo_export_import(void); - static void amdgpu_bo_metadata(void); - static void amdgpu_bo_map_unmap(void); +@@ -49,6 +50,7 @@ static void amdgpu_bo_map_unmap(void); + static void amdgpu_memory_alloc(void); + static void amdgpu_mem_fail_alloc(void); static void amdgpu_get_fb_id_and_handle(void); -- +static void amdgpu_bo_direct_gma(void); CU_TestInfo bo_tests[] = { { "Export/Import", amdgpu_bo_export_import }, -@@ -56,6 +57,7 @@ CU_TestInfo bo_tests[] = { - #endif - { "CPU map/unmap", amdgpu_bo_map_unmap }, +@@ -57,6 +59,7 @@ CU_TestInfo bo_tests[] = { + { "Memory alloc Test", amdgpu_memory_alloc }, + { "Memory fail alloc Test", amdgpu_mem_fail_alloc }, { "GET FB_ID AND FB_HANDLE", amdgpu_get_fb_id_and_handle }, + { "Direct GMA", amdgpu_bo_direct_gma }, CU_TEST_INFO_NULL, }; -@@ -217,3 +219,63 @@ static void amdgpu_get_fb_id_and_handle(void) - CU_ASSERT_EQUAL(r, 0); +@@ -219,6 +222,66 @@ static void amdgpu_get_fb_id_and_handle(void) CU_ASSERT_NOT_EQUAL(output.buf_handle, 0); } -+ + +#define TEST_LOOP 20 +static void amdgpu_bo_direct_gma(void) +{ @@ -102,6 +101,9 @@ index 83f42a9..930a073 100644 + } + } +} ++ + static void amdgpu_memory_alloc(void) + { + amdgpu_bo_handle bo; -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0022-amdgpu-add-new-semaphore-support-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0022-amdgpu-add-new-semaphore-support-v2.patch index 090147da..43b37a98 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0022-amdgpu-add-new-semaphore-support-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0022-amdgpu-add-new-semaphore-support-v2.patch @@ -1,7 +1,7 @@ -From 64a09d85da3869bf77a0b70fd1709f654ba3582d Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Thu, 22 Sep 2016 14:50:16 +0800 -Subject: [PATCH 22/39] amdgpu: add new semaphore support v2 +From c18acb08e7d948c3bb06d1737a4121b77acb46a6 Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Mon, 18 Dec 2017 15:32:27 +0500 +Subject: [PATCH] amdgpu: add new semaphore support v2 v2: 612336476adaffdd715fcc74c5aabceee8d53add @@ -19,17 +19,19 @@ Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Flora Cui <Flora.Cui@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Awais Belal <awais_belal@mentor.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu.h | 74 +++++++++++++++++++++++++++++++++++++++ amdgpu/amdgpu_cs.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++++ - include/drm/amdgpu_drm.h | 30 ++++++++++++++++ - 3 files changed, 195 insertions(+) + include/drm/amdgpu_drm.h | 31 +++++++++++++++++ + 3 files changed, 196 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index e7a566f..bff3252 100644 +index 423ad28..5247498 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -141,6 +141,12 @@ typedef struct amdgpu_va *amdgpu_va_handle; +@@ -146,6 +146,12 @@ typedef struct amdgpu_va *amdgpu_va_handle; */ typedef struct amdgpu_semaphore *amdgpu_semaphore_handle; @@ -42,7 +44,7 @@ index e7a566f..bff3252 100644 /*--------------------------------------------------------------------------*/ /* -------------------------- Structures ---------------------------------- */ /*--------------------------------------------------------------------------*/ -@@ -1578,6 +1584,74 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, +@@ -1616,6 +1622,74 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); /** @@ -118,7 +120,7 @@ index e7a566f..bff3252 100644 * * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c -index dfba875..8675806 100644 +index 46dffe1..9f21681 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -25,6 +25,8 @@ @@ -130,7 +132,7 @@ index dfba875..8675806 100644 #include <stdlib.h> #include <stdio.h> #include <string.h> -@@ -597,6 +599,95 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem) +@@ -606,6 +608,95 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem) return amdgpu_cs_unreference_sem(sem); } @@ -223,33 +225,37 @@ index dfba875..8675806 100644 + return 0; +} + - int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, - uint32_t *handle) - { + int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev, + uint32_t flags, + uint32_t *handle) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index b515809..6cf8c1b 100644 +index 43bb2f5..910f200 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -52,7 +52,9 @@ extern "C" { - #define DRM_AMDGPU_GEM_USERPTR 0x11 - #define DRM_AMDGPU_WAIT_FENCES 0x12 +@@ -54,7 +54,9 @@ extern "C" { #define DRM_AMDGPU_VM 0x13 + #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 + #define DRM_AMDGPU_SCHED 0x15 + /* hybrid specific ioctls */ -+#define DRM_AMDGPU_SEM 0x5b - #define DRM_AMDGPU_GEM_DGMA 0x5c - #define DRM_AMDGPU_FREESYNC 0x5d ++#define DRM_AMDGPU_SEM 0x5b + #define DRM_AMDGPU_GEM_DGMA 0x5c + #define DRM_AMDGPU_FREESYNC 0x5d #define DRM_AMDGPU_GEM_FIND_BO 0x5f -@@ -74,6 +76,7 @@ extern "C" { +@@ -75,9 +77,11 @@ extern "C" { + #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) + #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) + #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) ++ /* hybrid specific ioctls */ - #define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma) + #define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma) #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) -+#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem) - #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) ++#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem) + #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) #define AMDGPU_GEM_DOMAIN_CPU 0x1 -@@ -227,6 +230,33 @@ union drm_amdgpu_vm { - struct drm_amdgpu_vm_out out; +@@ -259,6 +263,33 @@ union drm_amdgpu_sched { + struct drm_amdgpu_sched_in in; }; +/* sync file related */ @@ -284,4 +290,3 @@ index b515809..6cf8c1b 100644 * number of reasons and have fallback path that do not use userptr to -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0024-test-case-for-export-import-sem.patch b/meta-v1000/recipes-graphics/drm/libdrm/0024-test-case-for-export-import-sem.patch index 5c11dc9d..fbf31d82 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0024-test-case-for-export-import-sem.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0024-test-case-for-export-import-sem.patch @@ -1,7 +1,7 @@ -From f7384045361d01f28ccf1c2772680a1630fc5d6d Mon Sep 17 00:00:00 2001 -From: David Mao <david.mao@amd.com> -Date: Mon, 23 Jan 2017 11:31:58 +0800 -Subject: [PATCH 24/39] test case for export/import sem +From 317f44faa8c3a645134147f1fafb5805a4d98159 Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Mon, 18 Dec 2017 15:37:24 +0500 +Subject: [PATCH] test case for export/import sem Test covers basic functionality includes create/destroy/import/export/wait/signal @@ -9,28 +9,29 @@ Change-Id: I8a8d767e5ef1889f8ac214fef98befba83969d8d Signed-off-by: David Mao <david.mao@amd.com> Signed-off-by: Flora Cui <Flora.Cui@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> + +Signed-off-by: Awais Belal <awais_belal@mentor.com> --- - tests/amdgpu/basic_tests.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 60 insertions(+) + tests/amdgpu/basic_tests.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 59 insertions(+) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 41a702d..1807538 100644 +index 520f1c96..9f6331f2 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c -@@ -504,6 +504,8 @@ static void amdgpu_semaphore_test(void) - uint32_t expired; +@@ -545,6 +545,8 @@ static void amdgpu_semaphore_test(void) + uint32_t sdma_nop, gfx_nop; amdgpu_bo_list_handle bo_list[2]; amdgpu_va_handle va_handle[2]; + amdgpu_sem_handle sem_handle, sem_handle_import; + int fd; int r, i; - r = amdgpu_cs_create_semaphore(&sem); -@@ -604,6 +606,64 @@ static void amdgpu_semaphore_test(void) - 500000000, 0, &expired); + if (family_id == AMDGPU_FAMILY_SI) { +@@ -654,6 +656,63 @@ static void amdgpu_semaphore_test(void) CU_ASSERT_EQUAL(r, 0); CU_ASSERT_EQUAL(expired, true); -+ + + /* 3. export/import sem test */ + r = amdgpu_cs_create_sem(device_handle, &sem_handle); + CU_ASSERT_EQUAL(r, 0); @@ -92,5 +93,5 @@ index 41a702d..1807538 100644 r = amdgpu_bo_unmap_and_free(ib_result_handle[i], va_handle[i], ib_result_mc_address[i], 4096); -- -2.7.4 +2.11.1 diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0025-amdgpu-Sparse-resource-support-for-Vulkan-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0025-amdgpu-Sparse-resource-support-for-Vulkan-v2.patch index 2a8c1721..60cb6cd9 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0025-amdgpu-Sparse-resource-support-for-Vulkan-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0025-amdgpu-Sparse-resource-support-for-Vulkan-v2.patch @@ -29,19 +29,20 @@ Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu.h | 22 +++++++++++ - amdgpu/amdgpu_bo.c | 101 +++++++++++++++++++++++++++++++++++++++++++++++ + amdgpu/amdgpu_bo.c | 100 +++++++++++++++++++++++++++++++++++++++++++++++ amdgpu/amdgpu_device.c | 11 ++++++ amdgpu/amdgpu_internal.h | 11 ++++++ amdgpu/amdgpu_vamgr.c | 29 ++++++++++++++ - 5 files changed, 174 insertions(+) + 5 files changed, 173 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index a9ef5ca..ade6d37 100644 +index f373be0..df0d88c 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -1479,6 +1479,28 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, +@@ -1517,6 +1517,28 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, uint32_t ops); /** @@ -59,22 +60,22 @@ index a9ef5ca..ade6d37 100644 + * <0 - Negative POSIX Error code + */ +int amdgpu_bo_va_op_refcounted(amdgpu_device_handle dev, -+ amdgpu_bo_handle bo, -+ uint64_t offset, -+ uint64_t size, -+ uint64_t addr, -+ uint64_t flags, -+ uint32_t ops); ++ amdgpu_bo_handle bo, ++ uint64_t offset, ++ uint64_t size, ++ uint64_t addr, ++ uint64_t flags, ++ uint32_t ops); + +/** * Reserve the virtual address range for SVM support * * \param amdgpu_device_handle diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 5a9cdbe2..9534c40 100644 +index 2ea9a0f..bfcdd07 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c -@@ -968,3 +968,104 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, +@@ -972,3 +972,103 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, return r; } @@ -178,15 +179,14 @@ index 5a9cdbe2..9534c40 100644 + pthread_mutex_unlock(&dev->remap_mutex); + return r; +} -+ diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index f95f163..03843b6 100644 +index e21ee8e..854c8f3 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c -@@ -131,11 +131,19 @@ int amdgpu_get_auth(int fd, int *auth) +@@ -130,11 +130,19 @@ int amdgpu_get_auth(int fd, int *auth) + static void amdgpu_device_free_internal(amdgpu_device_handle dev) { - const struct amdgpu_asic_id *id; + struct amdgpu_va_remap* vao; amdgpu_vamgr_deinit(&dev->vamgr_32); amdgpu_vamgr_deinit(&dev->vamgr); @@ -196,14 +196,14 @@ index f95f163..03843b6 100644 + + pthread_mutex_destroy(&dev->remap_mutex); + LIST_FOR_EACH_ENTRY(vao, &dev->remap_list, list) { -+ list_del(&vao->list); -+ free(vao); ++ list_del(&vao->list); ++ free(vao); + } + util_hash_table_remove(fd_tab, UINT_TO_PTR(dev->fd)); close(dev->fd); if ((dev->flink_fd >= 0) && (dev->fd != dev->flink_fd)) -@@ -281,6 +289,9 @@ int amdgpu_device_initialize(int fd, +@@ -290,6 +298,9 @@ int amdgpu_device_initialize(int fd, dev->svm_allocated = false; @@ -214,11 +214,11 @@ index f95f163..03843b6 100644 *minor_version = dev->minor_version; *device_handle = dev; diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 3d83c1a..b39f47a 100644 +index e284d91..64e9062 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h -@@ -80,6 +80,14 @@ struct amdgpu_asic_id { - char *marketing_name; +@@ -72,6 +72,14 @@ struct amdgpu_va { + struct amdgpu_bo_va_mgr *vamgr; }; +struct amdgpu_va_remap{ @@ -232,8 +232,8 @@ index 3d83c1a..b39f47a 100644 struct amdgpu_device { atomic_t refcount; int fd; -@@ -103,6 +111,9 @@ struct amdgpu_device { - struct amdgpu_bo_va_mgr vamgr_32; +@@ -98,6 +106,9 @@ struct amdgpu_device { + struct amdgpu_bo_va_mgr vamgr_high_32; /** svm range allocated */ bool svm_allocated; + /** The VA remapped list*/ @@ -243,10 +243,10 @@ index 3d83c1a..b39f47a 100644 struct amdgpu_bo { diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 63124a4..5c91d58 100644 +index 2af0989..9bdb52e 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c -@@ -475,9 +475,38 @@ int amdgpu_va_range_alloc_in_range(amdgpu_device_handle dev, +@@ -457,9 +457,38 @@ int amdgpu_va_range_alloc_in_range(amdgpu_device_handle dev, int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) { @@ -287,4 +287,3 @@ index 63124a4..5c91d58 100644 va_range_handle->size); -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0026-tests-amdgpu-add-uvd-enc-unit-tests-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0026-tests-amdgpu-add-uvd-enc-unit-tests-v2.patch deleted file mode 100644 index 63fcd42b..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0026-tests-amdgpu-add-uvd-enc-unit-tests-v2.patch +++ /dev/null @@ -1,387 +0,0 @@ -From 71b1a43633da6dd72be6aba64aa615917d378d16 Mon Sep 17 00:00:00 2001 -From: Leo Liu <leo.liu@amd.com> -Date: Wed, 11 Jan 2017 14:03:03 -0500 -Subject: [PATCH 26/39] tests/amdgpu: add uvd enc unit tests v2 - -v2: -2fc4b7adae824313a169fc33e80aa62c1105be99 -[Ken Wang] -fix test failure on pre-vega10 card (part) - -Signed-off-by: Leo Liu <leo.liu@amd.com> -Acked-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> -Signed-off-by: Avinash M N <avimn@amd.com> ---- - tests/amdgpu/Makefile.am | 1 + - tests/amdgpu/amdgpu_test.c | 6 + - tests/amdgpu/amdgpu_test.h | 15 +++ - tests/amdgpu/uvd_enc_tests.c | 303 +++++++++++++++++++++++++++++++++++++++++++ - 4 files changed, 325 insertions(+) - create mode 100644 tests/amdgpu/uvd_enc_tests.c - -diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am -index 9e08578..13b3dc8 100644 ---- a/tests/amdgpu/Makefile.am -+++ b/tests/amdgpu/Makefile.am -@@ -27,4 +27,5 @@ amdgpu_test_SOURCES = \ - vce_tests.c \ - vce_ib.h \ - frame.h \ -+ uvd_enc_tests.c \ - vcn_tests.c -diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c -index 1d44b09..032cc0d 100644 ---- a/tests/amdgpu/amdgpu_test.c -+++ b/tests/amdgpu/amdgpu_test.c -@@ -86,6 +86,12 @@ static CU_SuiteInfo suites[] = { - .pTests = vce_tests, - }, - { -+ .pName = "UVD ENC Tests", -+ .pInitFunc = suite_uvd_enc_tests_init, -+ .pCleanupFunc = suite_uvd_enc_tests_clean, -+ .pTests = uvd_enc_tests, -+ }, -+ { - .pName = "VCN Tests", - .pInitFunc = suite_vcn_tests_init, - .pCleanupFunc = suite_vcn_tests_clean, -diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h -index c75a07a..042672f 100644 ---- a/tests/amdgpu/amdgpu_test.h -+++ b/tests/amdgpu/amdgpu_test.h -@@ -105,6 +105,21 @@ int suite_vce_tests_clean(); - extern CU_TestInfo vce_tests[]; - - /** -+ * Initialize uvd enc test suite -+ */ -+int suite_uvd_enc_tests_init(); -+ -+/** -+ * Deinitialize uvd enc test suite -+ */ -+int suite_uvd_enc_tests_clean(); -+ -+/** -+ * Tests in uvd enc test suite -+ */ -+extern CU_TestInfo uvd_enc_tests[]; -+ -+/** - + * Initialize vcn test suite - + */ - int suite_vcn_tests_init(); -diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c -new file mode 100644 -index 0000000..81318df ---- /dev/null -+++ b/tests/amdgpu/uvd_enc_tests.c -@@ -0,0 +1,303 @@ -+/* -+ * Copyright 2017 Advanced Micro Devices, Inc. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included in -+ * all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ * -+*/ -+ -+#ifdef HAVE_CONFIG_H -+#include "config.h" -+#endif -+ -+#include <stdio.h> -+#include <inttypes.h> -+ -+#include "CUnit/Basic.h" -+ -+#include "util_math.h" -+ -+#include "amdgpu_test.h" -+#include "amdgpu_drm.h" -+#include "amdgpu_internal.h" -+ -+#define IB_SIZE 4096 -+#define MAX_RESOURCES 16 -+ -+struct amdgpu_uvd_enc_bo { -+ amdgpu_bo_handle handle; -+ amdgpu_va_handle va_handle; -+ uint64_t addr; -+ uint64_t size; -+ uint8_t *ptr; -+}; -+ -+static amdgpu_device_handle device_handle; -+static uint32_t major_version; -+static uint32_t minor_version; -+static uint32_t family_id; -+ -+static amdgpu_context_handle context_handle; -+static amdgpu_bo_handle ib_handle; -+static amdgpu_va_handle ib_va_handle; -+static uint64_t ib_mc_address; -+static uint32_t *ib_cpu; -+ -+static amdgpu_bo_handle resources[MAX_RESOURCES]; -+static unsigned num_resources; -+ -+static void amdgpu_cs_uvd_enc_create(void); -+static void amdgpu_cs_uvd_enc_encode(void); -+static void amdgpu_cs_uvd_enc_destroy(void); -+ -+CU_TestInfo uvd_enc_tests[] = { -+ { "UVD ENC create", amdgpu_cs_uvd_enc_create }, -+ { "UVD ENC encode", amdgpu_cs_uvd_enc_encode }, -+ { "UVD ENC destroy", amdgpu_cs_uvd_enc_destroy }, -+ CU_TEST_INFO_NULL, -+}; -+ -+int suite_uvd_enc_tests_init(void) -+{ -+ int r; -+ -+ r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, -+ &minor_version, &device_handle); -+ if (r) -+ return CUE_SINIT_FAILED; -+ -+ family_id = device_handle->info.family_id; -+ -+ if (family_id < AMDGPU_FAMILY_AI) { -+ -+ printf("\n\nThe ASIC NOT support UVD ENC, all sub-tests will pass\n"); -+ -+ return CUE_SUCCESS; -+ } -+ -+ r = amdgpu_cs_ctx_create(device_handle, &context_handle); -+ if (r) -+ return CUE_SINIT_FAILED; -+ -+ r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096, -+ AMDGPU_GEM_DOMAIN_GTT, 0, -+ &ib_handle, (void**)&ib_cpu, -+ &ib_mc_address, &ib_va_handle); -+ if (r) -+ return CUE_SINIT_FAILED; -+ -+ return CUE_SUCCESS; -+} -+ -+int suite_uvd_enc_tests_clean(void) -+{ -+ int r; -+ -+ if (family_id < AMDGPU_FAMILY_AI) { -+ -+ r = amdgpu_device_deinitialize(device_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ -+ return CUE_SUCCESS; -+ } else { -+ -+ r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, -+ ib_mc_address, IB_SIZE); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ -+ r = amdgpu_cs_ctx_free(context_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ -+ r = amdgpu_device_deinitialize(device_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ } -+ -+ return CUE_SUCCESS; -+} -+ -+static int submit(unsigned ndw, unsigned ip) -+{ -+ struct amdgpu_cs_request ibs_request = {0}; -+ struct amdgpu_cs_ib_info ib_info = {0}; -+ struct amdgpu_cs_fence fence_status = {0}; -+ uint32_t expired; -+ int r; -+ -+ ib_info.ib_mc_address = ib_mc_address; -+ ib_info.size = ndw; -+ -+ ibs_request.ip_type = ip; -+ -+ r = amdgpu_bo_list_create(device_handle, num_resources, resources, -+ NULL, &ibs_request.resources); -+ if (r) -+ return r; -+ -+ ibs_request.number_of_ibs = 1; -+ ibs_request.ibs = &ib_info; -+ ibs_request.fence_info.handle = NULL; -+ -+ r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); -+ if (r) -+ return r; -+ -+ r = amdgpu_bo_list_destroy(ibs_request.resources); -+ if (r) -+ return r; -+ -+ fence_status.context = context_handle; -+ fence_status.ip_type = ip; -+ fence_status.fence = ibs_request.seq_no; -+ -+ r = amdgpu_cs_query_fence_status(&fence_status, -+ AMDGPU_TIMEOUT_INFINITE, -+ 0, &expired); -+ if (r) -+ return r; -+ -+ return 0; -+} -+ -+static void alloc_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo, -+ unsigned size, unsigned domain) -+{ -+ struct amdgpu_bo_alloc_request req = {0}; -+ amdgpu_bo_handle buf_handle; -+ amdgpu_va_handle va_handle; -+ uint64_t va = 0; -+ int r; -+ -+ req.alloc_size = ALIGN(size, 4096); -+ req.preferred_heap = domain; -+ r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); -+ CU_ASSERT_EQUAL(r, 0); -+ r = amdgpu_va_range_alloc(device_handle, -+ amdgpu_gpu_va_range_general, -+ req.alloc_size, 1, 0, &va, -+ &va_handle, 0); -+ CU_ASSERT_EQUAL(r, 0); -+ r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, -+ AMDGPU_VA_OP_MAP); -+ CU_ASSERT_EQUAL(r, 0); -+ uvd_enc_bo->addr = va; -+ uvd_enc_bo->handle = buf_handle; -+ uvd_enc_bo->size = req.alloc_size; -+ uvd_enc_bo->va_handle = va_handle; -+ r = amdgpu_bo_cpu_map(uvd_enc_bo->handle, (void **)&uvd_enc_bo->ptr); -+ CU_ASSERT_EQUAL(r, 0); -+ memset(uvd_enc_bo->ptr, 0, size); -+ r = amdgpu_bo_cpu_unmap(uvd_enc_bo->handle); -+ CU_ASSERT_EQUAL(r, 0); -+} -+ -+static void free_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo) -+{ -+ int r; -+ -+ r = amdgpu_bo_va_op(uvd_enc_bo->handle, 0, uvd_enc_bo->size, -+ uvd_enc_bo->addr, 0, AMDGPU_VA_OP_UNMAP); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_va_range_free(uvd_enc_bo->va_handle); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_free(uvd_enc_bo->handle); -+ CU_ASSERT_EQUAL(r, 0); -+ memset(uvd_enc_bo, 0, sizeof(*uvd_enc_bo)); -+} -+ -+static void amdgpu_cs_uvd_enc_create(void) -+{ -+ struct amdgpu_uvd_enc_bo sw_ctx; -+ int len, r; -+ -+ if (family_id < AMDGPU_FAMILY_AI) -+ return; -+ -+ num_resources = 0; -+ alloc_resource(&sw_ctx, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); -+ resources[num_resources++] = sw_ctx.handle; -+ resources[num_resources++] = ib_handle; -+ -+ len = 0; -+ ib_cpu[len++] = 0x00000018; -+ ib_cpu[len++] = 0x00000001; /* session info */ -+ ib_cpu[len++] = 0x00000001; -+ ib_cpu[len++] = 0x00000000; -+ ib_cpu[len++] = sw_ctx.addr >> 32; -+ ib_cpu[len++] = sw_ctx.addr; -+ -+ ib_cpu[len++] = 0x00000014; -+ ib_cpu[len++] = 0x00000002; /* task info */ -+ ib_cpu[len++] = 0x0000001c; -+ ib_cpu[len++] = 0x00000000; -+ ib_cpu[len++] = 0x00000000; -+ -+ ib_cpu[len++] = 0x00000008; -+ ib_cpu[len++] = 0x08000001; /* op initialize */ -+ -+ r = submit(len, AMDGPU_HW_IP_UVD_ENC); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ free_resource(&sw_ctx); -+} -+ -+static void amdgpu_cs_uvd_enc_encode(void) -+{ -+ /* TODO */ -+} -+ -+static void amdgpu_cs_uvd_enc_destroy(void) -+{ -+ struct amdgpu_uvd_enc_bo sw_ctx; -+ int len, r; -+ -+ if (family_id < AMDGPU_FAMILY_AI) -+ return; -+ -+ num_resources = 0; -+ alloc_resource(&sw_ctx, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); -+ resources[num_resources++] = sw_ctx.handle; -+ resources[num_resources++] = ib_handle; -+ -+ len = 0; -+ ib_cpu[len++] = 0x00000018; -+ ib_cpu[len++] = 0x00000001; /* session info */ -+ ib_cpu[len++] = 0x00000001; -+ ib_cpu[len++] = 0x00000000; -+ ib_cpu[len++] = sw_ctx.addr >> 32; -+ ib_cpu[len++] = sw_ctx.addr; -+ -+ ib_cpu[len++] = 0x00000014; -+ ib_cpu[len++] = 0x00000002; /* task info */ -+ ib_cpu[len++] = 0xffffffff; -+ ib_cpu[len++] = 0x00000000; -+ ib_cpu[len++] = 0x00000000; -+ -+ ib_cpu[len++] = 0x00000008; -+ ib_cpu[len++] = 0x08000002; /* op close session */ -+ -+ r = submit(len, AMDGPU_HW_IP_UVD_ENC); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ free_resource(&sw_ctx); -+} --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0027-tests-amdgpu-add-uve-ib-header.patch b/meta-v1000/recipes-graphics/drm/libdrm/0027-tests-amdgpu-add-uve-ib-header.patch deleted file mode 100644 index 154ce142..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0027-tests-amdgpu-add-uve-ib-header.patch +++ /dev/null @@ -1,344 +0,0 @@ -From 0af63ae477629806586c8e26480e48febf4fa4f9 Mon Sep 17 00:00:00 2001 -From: Boyuan Zhang <boyuan.zhang@amd.com> -Date: Mon, 13 Feb 2017 09:43:42 -0500 -Subject: [PATCH 27/39] tests/amdgpu: add uve ib header - -Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> -Reviewed-by: Leo Liu <leo.liu@amd.com> ---- - tests/amdgpu/uve_ib.h | 323 ++++++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 323 insertions(+) - create mode 100644 tests/amdgpu/uve_ib.h - -diff --git a/tests/amdgpu/uve_ib.h b/tests/amdgpu/uve_ib.h -new file mode 100644 -index 0000000..c24b9e8 ---- /dev/null -+++ b/tests/amdgpu/uve_ib.h -@@ -0,0 +1,323 @@ -+/* -+ * Copyright 2017 Advanced Micro Devices, Inc. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included in -+ * all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ * -+*/ -+ -+#ifndef _uve_ib_h_ -+#define _uve_ib_h_ -+ -+static const uint32_t uve_session_info[] = { -+ 0x00000018, -+ 0x00000001, -+ 0x00000001, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_task_info[] = { -+ 0x00000014, -+ 0x00000002, -+}; -+ -+static const uint32_t uve_session_init[] = { -+ 0x00000068, -+ 0x00000003, -+ 0x00000000, -+ 0x000000c0, -+ 0x00000080, -+ 0x00000000, -+ 0x00000000, -+ 0x00000001, -+ 0x00000002, -+ 0x000000c0, -+ 0x00000080, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_layer_ctrl[] = { -+ 0x00000010, -+ 0x00000004, -+ 0x00000001, -+ 0x00000001, -+}; -+ -+static const uint32_t uve_layer_select[] = { -+ 0x0000000c, -+ 0x00000005, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_slice_ctrl[] = { -+ 0x00000014, -+ 0x00000006, -+ 0x00000000, -+ 0x00000008, -+ 0x00000008, -+}; -+ -+static const uint32_t uve_spec_misc[] = { -+ 0x00000024, -+ 0x00000007, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000004, -+ 0x00000000, -+ 0x00000005, -+}; -+ -+static const uint32_t uve_rc_session_init[] = { -+ 0x00000010, -+ 0x00000008, -+ 0x00000000, -+ 0x00000040, -+}; -+ -+static const uint32_t uve_rc_layer_init[] = { -+ 0x00000028, -+ 0x00000009, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_hw_spec[] = { -+ 0x0000007c, -+ 0x0000000b, -+ 0x00000002, -+ 0x00000000, -+ 0x00000001, -+ 0x00000001, -+ 0x00000001, -+ 0x00000001, -+ 0x00000001, -+ 0x00000010, -+ 0x00000010, -+ 0x00000010, -+ 0x00000010, -+ 0x00000008, -+ 0x00000008, -+ 0x00000010, -+ 0x00000010, -+ 0x00000000, -+ 0x00000002, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000001, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000001, -+ 0x00000001, -+}; -+ -+static const uint32_t uve_deblocking_filter[] = { -+ 0x00000020, -+ 0x0000000f, -+ 0x00000001, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_feedback_buffer[] = { -+ 0x00000014, -+ 0x00000014, -+}; -+ -+/* TODO - Slice Header*/ -+static const uint32_t uve_slice_header[] = { -+ 0x000000c8, -+ 0x0000000c, -+ 0x26010000, -+ 0x40000000, -+ 0x60000000, -+ 0x80000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000002, -+ 0x00000010, -+ 0x00000003, -+ 0x00000000, -+ 0x00000002, -+ 0x00000002, -+ 0x00000004, -+ 0x00000000, -+ 0x00000001, -+ 0x00000000, -+ 0x00000002, -+ 0x00000003, -+ 0x00000005, -+ 0x00000000, -+ 0x00000002, -+ 0x00000001, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_encode_param[] = { -+ 0x00000000, -+ 0x00000000, -+ 0x000000a0, -+ 0x00000080, -+ 0x00000000, -+ 0x00000000, -+ 0x00000002, -+ 0xffffffff, -+ 0xffffffff, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_quality_param[] = { -+ 0x00000014, -+ 0x0000000e, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_intra_refresh[] = { -+ 0x00000014, -+ 0x00000010, -+ 0x00000000, -+ 0x00000000, -+ 0x00000004, -+}; -+ -+static const uint32_t uve_reconstructed_pic_output[] = { -+ 0x00000020, -+ 0x00000011, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_ctx_buffer[] = { -+ 0x00000010, -+ 0x00000012, -+}; -+ -+static const uint32_t uve_bitstream_buffer[] = { -+ 0x00000014, -+ 0x00000013, -+}; -+ -+static const uint32_t uve_rc_per_pic[] = { -+ 0x00000024, -+ 0x0000000a, -+ 0x0000001a, -+ 0x00000014, -+ 0x0000002D, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_op_init[] = { -+ 0x00000008, -+ 0x08000001, -+}; -+ -+static const uint32_t uve_op_close[] = { -+ 0x00000008, -+ 0x08000002, -+}; -+ -+static const uint32_t uve_op_encode[] = { -+ 0x00000008, -+ 0x08000003, -+}; -+ -+static const uint32_t uve_op_init_rc[] = { -+ 0x00000008, -+ 0x08000004, -+}; -+#endif /*_uve_ib_h*/ --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0028-tests-amdgpu-implement-hevc-encode-test-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0028-tests-amdgpu-implement-hevc-encode-test-v2.patch deleted file mode 100644 index e3adfe55..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0028-tests-amdgpu-implement-hevc-encode-test-v2.patch +++ /dev/null @@ -1,375 +0,0 @@ -From b37b4f050ed21e52cb2a3e14105d4f4a7bb7be15 Mon Sep 17 00:00:00 2001 -From: Boyuan Zhang <boyuan.zhang@amd.com> -Date: Mon, 13 Feb 2017 09:54:32 -0500 -Subject: [PATCH 28/39] tests/amdgpu: implement hevc encode test v2 - -v2: -2fc4b7adae824313a169fc33e80aa62c1105be99 -[Ken Wang] -fix test failure on pre-vega10 card (part) - -Change-Id: I3d77e1e7f60b2b806a9134f94ba851cee699f4a9 -Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> -Reviewed-by: Leo Liu <leo.liu@amd.com> -Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> ---- - tests/amdgpu/frame.h | 2 +- - tests/amdgpu/uvd_enc_tests.c | 261 ++++++++++++++++++++++++++++++++++++++----- - 2 files changed, 233 insertions(+), 30 deletions(-) - -diff --git a/tests/amdgpu/frame.h b/tests/amdgpu/frame.h -index 4c946c2..335401c 100644 ---- a/tests/amdgpu/frame.h -+++ b/tests/amdgpu/frame.h -@@ -24,7 +24,7 @@ - #ifndef _frame_h_ - #define _frame_h_ - --const uint8_t frame[] = { -+static const uint8_t frame[] = { - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, - 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xaa, 0xaa, 0xaa, -diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c -index 81318df..fee0112 100644 ---- a/tests/amdgpu/uvd_enc_tests.c -+++ b/tests/amdgpu/uvd_enc_tests.c -@@ -35,6 +35,8 @@ - #include "amdgpu_test.h" - #include "amdgpu_drm.h" - #include "amdgpu_internal.h" -+#include "frame.h" -+#include "uve_ib.h" - - #define IB_SIZE 4096 - #define MAX_RESOURCES 16 -@@ -47,6 +49,16 @@ struct amdgpu_uvd_enc_bo { - uint8_t *ptr; - }; - -+struct amdgpu_uvd_enc { -+ unsigned width; -+ unsigned height; -+ struct amdgpu_uvd_enc_bo session; -+ struct amdgpu_uvd_enc_bo vbuf; -+ struct amdgpu_uvd_enc_bo bs; -+ struct amdgpu_uvd_enc_bo fb; -+ struct amdgpu_uvd_enc_bo cpb; -+}; -+ - static amdgpu_device_handle device_handle; - static uint32_t major_version; - static uint32_t minor_version; -@@ -58,15 +70,18 @@ static amdgpu_va_handle ib_va_handle; - static uint64_t ib_mc_address; - static uint32_t *ib_cpu; - -+static struct amdgpu_uvd_enc enc; - static amdgpu_bo_handle resources[MAX_RESOURCES]; - static unsigned num_resources; - - static void amdgpu_cs_uvd_enc_create(void); -+static void amdgpu_cs_uvd_enc_session_init(void); - static void amdgpu_cs_uvd_enc_encode(void); - static void amdgpu_cs_uvd_enc_destroy(void); - - CU_TestInfo uvd_enc_tests[] = { - { "UVD ENC create", amdgpu_cs_uvd_enc_create }, -+ { "UVD ENC session init", amdgpu_cs_uvd_enc_session_init }, - { "UVD ENC encode", amdgpu_cs_uvd_enc_encode }, - { "UVD ENC destroy", amdgpu_cs_uvd_enc_destroy }, - CU_TEST_INFO_NULL, -@@ -227,43 +242,235 @@ static void free_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo) - - static void amdgpu_cs_uvd_enc_create(void) - { -- struct amdgpu_uvd_enc_bo sw_ctx; - int len, r; - - if (family_id < AMDGPU_FAMILY_AI) - return; - -+ enc.width = 160; -+ enc.height = 128; -+ - num_resources = 0; -- alloc_resource(&sw_ctx, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); -- resources[num_resources++] = sw_ctx.handle; -+ alloc_resource(&enc.session, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); -+ resources[num_resources++] = enc.session.handle; - resources[num_resources++] = ib_handle; - - len = 0; -- ib_cpu[len++] = 0x00000018; -- ib_cpu[len++] = 0x00000001; /* session info */ -- ib_cpu[len++] = 0x00000001; -- ib_cpu[len++] = 0x00000000; -- ib_cpu[len++] = sw_ctx.addr >> 32; -- ib_cpu[len++] = sw_ctx.addr; -+ memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); -+ len += sizeof(uve_session_info) / 4; -+ ib_cpu[len++] = enc.session.addr >> 32; -+ ib_cpu[len++] = enc.session.addr; - -- ib_cpu[len++] = 0x00000014; -- ib_cpu[len++] = 0x00000002; /* task info */ -+ memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); -+ len += sizeof(uve_task_info) / 4; - ib_cpu[len++] = 0x0000001c; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - -- ib_cpu[len++] = 0x00000008; -- ib_cpu[len++] = 0x08000001; /* op initialize */ -+ memcpy((ib_cpu + len), uve_op_init, sizeof(uve_op_init)); -+ len += sizeof(uve_op_init) / 4; -+ -+ r = submit(len, AMDGPU_HW_IP_UVD_ENC); -+ CU_ASSERT_EQUAL(r, 0); -+} -+ -+static void check_result(struct amdgpu_uvd_enc *enc) -+{ -+ uint64_t sum; -+ uint32_t s = 20626; -+ uint32_t *ptr, size; -+ int i, j, r; -+ -+ r = amdgpu_bo_cpu_map(enc->fb.handle, (void **)&enc->fb.ptr); -+ CU_ASSERT_EQUAL(r, 0); -+ ptr = (uint32_t *)enc->fb.ptr; -+ size = ptr[6]; -+ r = amdgpu_bo_cpu_unmap(enc->fb.handle); -+ CU_ASSERT_EQUAL(r, 0); -+ r = amdgpu_bo_cpu_map(enc->bs.handle, (void **)&enc->bs.ptr); -+ CU_ASSERT_EQUAL(r, 0); -+ for (j = 0, sum = 0; j < size; ++j) -+ sum += enc->bs.ptr[j]; -+ CU_ASSERT_EQUAL(sum, s); -+ r = amdgpu_bo_cpu_unmap(enc->bs.handle); -+ CU_ASSERT_EQUAL(r, 0); -+ -+} -+ -+static void amdgpu_cs_uvd_enc_session_init(void) -+{ -+ int len, r; -+ -+ if (family_id < AMDGPU_FAMILY_AI) -+ return; -+ -+ num_resources = 0; -+ alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_GTT); -+ resources[num_resources++] = enc.fb.handle; -+ resources[num_resources++] = ib_handle; -+ -+ len = 0; -+ memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); -+ len += sizeof(uve_session_info) / 4; -+ ib_cpu[len++] = enc.session.addr >> 32; -+ ib_cpu[len++] = enc.session.addr; -+ -+ memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); -+ len += sizeof(uve_task_info) / 4; -+ ib_cpu[len++] = 0x000001c0; -+ ib_cpu[len++] = 0x00000001; -+ ib_cpu[len++] = 0x00000001; -+ -+ memcpy((ib_cpu + len), uve_session_init, sizeof(uve_session_init)); -+ len += sizeof(uve_session_init) / 4; -+ -+ memcpy((ib_cpu + len), uve_layer_ctrl, sizeof(uve_layer_ctrl)); -+ len += sizeof(uve_layer_ctrl) / 4; -+ -+ memcpy((ib_cpu + len), uve_layer_select, sizeof(uve_layer_select)); -+ len += sizeof(uve_layer_select) / 4; -+ -+ memcpy((ib_cpu + len), uve_slice_ctrl, sizeof(uve_slice_ctrl)); -+ len += sizeof(uve_slice_ctrl) / 4; -+ -+ memcpy((ib_cpu + len), uve_spec_misc, sizeof(uve_spec_misc)); -+ len += sizeof(uve_spec_misc) / 4; -+ -+ memcpy((ib_cpu + len), uve_rc_session_init, sizeof(uve_rc_session_init)); -+ len += sizeof(uve_rc_session_init) / 4; -+ -+ memcpy((ib_cpu + len), uve_rc_layer_init, sizeof(uve_rc_layer_init)); -+ len += sizeof(uve_rc_layer_init) / 4; -+ -+ memcpy((ib_cpu + len), uve_hw_spec, sizeof(uve_hw_spec)); -+ len += sizeof(uve_hw_spec) / 4; -+ -+ memcpy((ib_cpu + len), uve_deblocking_filter, sizeof(uve_deblocking_filter)); -+ len += sizeof(uve_deblocking_filter) / 4; -+ -+ memcpy((ib_cpu + len), uve_feedback_buffer, sizeof(uve_feedback_buffer)); -+ len += sizeof(uve_feedback_buffer) / 4; -+ ib_cpu[len++] = enc.fb.addr >> 32; -+ ib_cpu[len++] = enc.fb.addr; -+ ib_cpu[len++] = 0x00000003; -+ -+ memcpy((ib_cpu + len), uve_op_init_rc, sizeof(uve_op_init_rc)); -+ len += sizeof(uve_op_init_rc) / 4; - - r = submit(len, AMDGPU_HW_IP_UVD_ENC); - CU_ASSERT_EQUAL(r, 0); - -- free_resource(&sw_ctx); -+ free_resource(&enc.fb); - } - - static void amdgpu_cs_uvd_enc_encode(void) - { -- /* TODO */ -+ int len, r, i; -+ uint64_t luma_offset, chroma_offset; -+ uint32_t vbuf_size, bs_size = 0x154000, cpb_size; -+ unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; -+ vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; -+ cpb_size = vbuf_size * 10; -+ -+ if (family_id < AMDGPU_FAMILY_AI) -+ return; -+ -+ num_resources = 0; -+ alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_VRAM); -+ resources[num_resources++] = enc.fb.handle; -+ alloc_resource(&enc.bs, bs_size, AMDGPU_GEM_DOMAIN_VRAM); -+ resources[num_resources++] = enc.bs.handle; -+ alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM); -+ resources[num_resources++] = enc.vbuf.handle; -+ alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM); -+ resources[num_resources++] = enc.cpb.handle; -+ resources[num_resources++] = ib_handle; -+ -+ r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ memset(enc.vbuf.ptr, 0, vbuf_size); -+ for (i = 0; i < enc.height; ++i) { -+ memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width); -+ enc.vbuf.ptr += ALIGN(enc.width, align); -+ } -+ for (i = 0; i < enc.height / 2; ++i) { -+ memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width); -+ enc.vbuf.ptr += ALIGN(enc.width, align); -+ } -+ -+ r = amdgpu_bo_cpu_unmap(enc.vbuf.handle); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ len = 0; -+ memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); -+ len += sizeof(uve_session_info) / 4; -+ ib_cpu[len++] = enc.session.addr >> 32; -+ ib_cpu[len++] = enc.session.addr; -+ -+ memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); -+ len += sizeof(uve_task_info) / 4; -+ ib_cpu[len++] = 0x00000210; -+ ib_cpu[len++] = 0x00000002; -+ ib_cpu[len++] = 0x00000001; -+ -+ memcpy((ib_cpu + len), uve_slice_header, sizeof(uve_slice_header)); -+ len += sizeof(uve_slice_header) / 4; -+ -+ unsigned luma_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16); -+ luma_offset = enc.vbuf.addr; -+ chroma_offset = luma_offset + luma_size; -+ ib_cpu[len++] = 0x00000088; -+ ib_cpu[len++] = 0x0000000d; -+ ib_cpu[len++] = 0x00018000; -+ ib_cpu[len++] = luma_offset >> 32; -+ ib_cpu[len++] = luma_offset; -+ ib_cpu[len++] = chroma_offset >> 32; -+ ib_cpu[len++] = chroma_offset; -+ memcpy((ib_cpu + len), uve_encode_param, sizeof(uve_encode_param)); -+ len += sizeof(uve_encode_param) / 4; -+ -+ memcpy((ib_cpu + len), uve_quality_param, sizeof(uve_quality_param)); -+ len += sizeof(uve_quality_param) / 4; -+ -+ memcpy((ib_cpu + len), uve_intra_refresh, sizeof(uve_intra_refresh)); -+ len += sizeof(uve_intra_refresh) / 4; -+ -+ memcpy((ib_cpu + len), uve_reconstructed_pic_output, sizeof(uve_reconstructed_pic_output)); -+ len += sizeof(uve_reconstructed_pic_output) / 4; -+ -+ memcpy((ib_cpu + len), uve_ctx_buffer, sizeof(uve_ctx_buffer)); -+ len += sizeof(uve_ctx_buffer) / 4; -+ ib_cpu[len++] = enc.cpb.addr >> 32; -+ ib_cpu[len++] = enc.cpb.addr; -+ -+ memcpy((ib_cpu + len), uve_bitstream_buffer, sizeof(uve_bitstream_buffer)); -+ len += sizeof(uve_bitstream_buffer) / 4; -+ ib_cpu[len++] = enc.bs.addr >> 32; -+ ib_cpu[len++] = enc.bs.addr; -+ ib_cpu[len++] = 0x00030000; -+ -+ memcpy((ib_cpu + len), uve_feedback_buffer, sizeof(uve_feedback_buffer)); -+ len += sizeof(uve_feedback_buffer) / 4; -+ ib_cpu[len++] = enc.fb.addr >> 32; -+ ib_cpu[len++] = enc.fb.addr; -+ ib_cpu[len++] = 0x00000003; -+ -+ memcpy((ib_cpu + len), uve_rc_per_pic, sizeof(uve_rc_per_pic)); -+ len += sizeof(uve_rc_per_pic) / 4; -+ -+ memcpy((ib_cpu + len), uve_op_encode, sizeof(uve_op_encode)); -+ len += sizeof(uve_op_encode) / 4; -+ -+ r = submit(len, AMDGPU_HW_IP_UVD_ENC); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ check_result(&enc); -+ -+ free_resource(&enc.fb); -+ free_resource(&enc.bs); -+ free_resource(&enc.vbuf); -+ free_resource(&enc.cpb); - } - - static void amdgpu_cs_uvd_enc_destroy(void) -@@ -275,29 +482,25 @@ static void amdgpu_cs_uvd_enc_destroy(void) - return; - - num_resources = 0; -- alloc_resource(&sw_ctx, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); -- resources[num_resources++] = sw_ctx.handle; - resources[num_resources++] = ib_handle; - - len = 0; -- ib_cpu[len++] = 0x00000018; -- ib_cpu[len++] = 0x00000001; /* session info */ -- ib_cpu[len++] = 0x00000001; -- ib_cpu[len++] = 0x00000000; -- ib_cpu[len++] = sw_ctx.addr >> 32; -- ib_cpu[len++] = sw_ctx.addr; -+ memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); -+ len += sizeof(uve_session_info) / 4; -+ ib_cpu[len++] = enc.session.addr >> 32; -+ ib_cpu[len++] = enc.session.addr; - -- ib_cpu[len++] = 0x00000014; -- ib_cpu[len++] = 0x00000002; /* task info */ -+ memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); -+ len += sizeof(uve_task_info) / 4; - ib_cpu[len++] = 0xffffffff; -- ib_cpu[len++] = 0x00000000; -+ ib_cpu[len++] = 0x00000004; - ib_cpu[len++] = 0x00000000; - -- ib_cpu[len++] = 0x00000008; -- ib_cpu[len++] = 0x08000002; /* op close session */ -+ memcpy((ib_cpu + len), uve_op_close, sizeof(uve_op_close)); -+ len += sizeof(uve_op_close) / 4; - - r = submit(len, AMDGPU_HW_IP_UVD_ENC); - CU_ASSERT_EQUAL(r, 0); - -- free_resource(&sw_ctx); -+ free_resource(&enc.session); - } --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0030-amdgpu-hybrid-add-a-flag-of-memory-allcation-from-to.patch b/meta-v1000/recipes-graphics/drm/libdrm/0030-amdgpu-hybrid-add-a-flag-of-memory-allcation-from-to.patch index 99f2f024..c0eeab0e 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0030-amdgpu-hybrid-add-a-flag-of-memory-allcation-from-to.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0030-amdgpu-hybrid-add-a-flag-of-memory-allcation-from-to.patch @@ -7,23 +7,23 @@ Subject: [PATCH 30/39] amdgpu: [hybrid] add a flag of memory allcation from Change-Id: I740c9f93a483b9cb728892963c7a0d6577819d59 Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- include/drm/amdgpu_drm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 216caa2..dfa7837 100644 +index a8f0c14..eb6f00e 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -103,6 +103,8 @@ extern "C" { +@@ -112,6 +112,8 @@ extern "C" { /* Hybrid specific */ /* Flag that the memory should be in SPARSE resource */ - #define AMDGPU_GEM_CREATE_SPARSE (1ULL << 29) + #define AMDGPU_GEM_CREATE_SPARSE (1ULL << 29) +/* Flag that the memory allocation should be from top of domain */ -+#define AMDGPU_GEM_CREATE_TOP_DOWN (1ULL << 30) ++#define AMDGPU_GEM_CREATE_TOP_DOWN (1ULL << 30) /* Flag that the memory allocation should be pinned */ - #define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) + #define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0032-amdgpu-add-interface-for-reserve-unserve-vmid-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0032-amdgpu-add-interface-for-reserve-unserve-vmid-v2.patch index 19fa1f93..31b235fd 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0032-amdgpu-add-interface-for-reserve-unserve-vmid-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0032-amdgpu-add-interface-for-reserve-unserve-vmid-v2.patch @@ -10,20 +10,20 @@ Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- - amdgpu/amdgpu.h | 13 +++++++++++++ + amdgpu/amdgpu.h | 14 ++++++++++++++ amdgpu/amdgpu_cs.c | 28 ++++++++++++++++++++++++++++ - 2 files changed, 41 insertions(+) + 2 files changed, 42 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 0a3063f..ddd250f 100644 +index 3ca923d..220663a 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -1645,6 +1645,19 @@ int amdgpu_cs_signal_sem(amdgpu_device_handle dev, - uint32_t ip_instance, - uint32_t ring, +@@ -1685,6 +1685,20 @@ int amdgpu_cs_signal_sem(amdgpu_device_handle dev, amdgpu_sem_handle sem); -+/** + + /** + * reserve vmid for this process + * + * \param dev - [in] Device handle. See #amdgpu_device_initialize() @@ -36,14 +36,16 @@ index 0a3063f..ddd250f 100644 + * \param dev - [in] Device handle. See #amdgpu_device_initialize() + */ +int amdgpu_cs_unreserved_vmid(amdgpu_device_handle dev); - - /** ++ ++/** * wait sem + * + * \param dev - [in] Device handle. See #amdgpu_device_initialize() diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c -index 8570714..e38ecab 100644 +index c23ff24..6e6db0e 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c -@@ -730,6 +730,34 @@ int amdgpu_cs_destroy_sem(amdgpu_device_handle dev, +@@ -739,6 +739,34 @@ int amdgpu_cs_destroy_sem(amdgpu_device_handle dev, return 0; } @@ -75,9 +77,8 @@ index 8570714..e38ecab 100644 + return r; +} + - int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, - uint32_t *handle) - { + int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev, + uint32_t flags, + uint32_t *handle) -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0033-amdgpu-HYBRID-add-AMDGPU_CAPABILITY_SSG_FLAG.patch b/meta-v1000/recipes-graphics/drm/libdrm/0033-amdgpu-HYBRID-add-AMDGPU_CAPABILITY_SSG_FLAG.patch index 4075363f..3babe504 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0033-amdgpu-HYBRID-add-AMDGPU_CAPABILITY_SSG_FLAG.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0033-amdgpu-HYBRID-add-AMDGPU_CAPABILITY_SSG_FLAG.patch @@ -9,23 +9,23 @@ Change-Id: Id52286984c8a43b77ad443799b267a6d0b23df54 Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- include/drm/amdgpu_drm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index dfa7837..8ced57d 100644 +index 4192dca..71261ab 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -964,6 +964,8 @@ struct drm_amdgpu_virtual_range { +@@ -1020,6 +1020,8 @@ struct drm_amdgpu_virtual_range { #define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) /* query direct gma capability */ #define AMDGPU_CAPABILITY_DIRECT_GMA_FLAG (1 << 1) +/* query ssg capability */ -+#define AMDGPU_CAPABILITY_SSG_FLAG (1 << 2) ++#define AMDGPU_CAPABILITY_SSG_FLAG (1 << 2) struct drm_amdgpu_capability { uint32_t flag; -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0034-tests-amdgpu-bypass-UVD-CS-tests-on-raven.patch b/meta-v1000/recipes-graphics/drm/libdrm/0034-tests-amdgpu-bypass-UVD-CS-tests-on-raven.patch deleted file mode 100644 index 21f00d15..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0034-tests-amdgpu-bypass-UVD-CS-tests-on-raven.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 61e501aaf6fd4545d7242b829f25b984fabc787c Mon Sep 17 00:00:00 2001 -From: Hawking Zhang <Hawking.Zhang@amd.com> -Date: Sat, 27 May 2017 13:40:45 +0800 -Subject: [PATCH 34/39] tests/amdgpu: bypass UVD CS tests on raven - -raven doesn't support UVD decode - -Change-Id: Ibc3a3a1b1007aaf7cf8de8b6ccd2457167f11fcb -Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> -Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> ---- - tests/amdgpu/cs_tests.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - -diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c -index 081ec9c..df55c70 100644 ---- a/tests/amdgpu/cs_tests.c -+++ b/tests/amdgpu/cs_tests.c -@@ -90,6 +90,11 @@ int suite_cs_tests_init(void) - chip_rev = device_handle->info.chip_rev; - chip_id = device_handle->info.chip_external_rev; - -+ if (family_id >= AMDGPU_FAMILY_RV) { -+ printf("\n\nThe ASIC NOT support UVD, all sub-tests will pass\n"); -+ return CUE_SUCCESS; -+ } -+ - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - if (r) - return CUE_SINIT_FAILED; -@@ -114,6 +119,9 @@ int suite_cs_tests_clean(void) - { - int r; - -+ if (family_id >= AMDGPU_FAMILY_RV) -+ return CUE_SUCCESS; -+ - r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, - ib_mc_address, IB_SIZE); - if (r) -@@ -192,6 +200,9 @@ static void amdgpu_cs_uvd_create(void) - void *msg; - int i, r; - -+ if (family_id >= AMDGPU_FAMILY_RV) -+ return; -+ - req.alloc_size = 4*1024; - req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; - -@@ -263,6 +274,9 @@ static void amdgpu_cs_uvd_decode(void) - uint8_t *ptr; - int i, r; - -+ if (family_id >= AMDGPU_FAMILY_RV) -+ return; -+ - req.alloc_size = 4*1024; /* msg */ - req.alloc_size += 4*1024; /* fb */ - if (family_id >= AMDGPU_FAMILY_VI) -@@ -402,6 +416,9 @@ static void amdgpu_cs_uvd_destroy(void) - void *msg; - int i, r; - -+ if (family_id >= AMDGPU_FAMILY_RV) -+ return; -+ - req.alloc_size = 4*1024; - req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; - --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0035-tests-amdgpu-bypass-UVD-ENC-tests-on-raven.patch b/meta-v1000/recipes-graphics/drm/libdrm/0035-tests-amdgpu-bypass-UVD-ENC-tests-on-raven.patch deleted file mode 100644 index 40b49190..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0035-tests-amdgpu-bypass-UVD-ENC-tests-on-raven.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 609397c048f572c618756a8379eb6b7fda7228da Mon Sep 17 00:00:00 2001 -From: Hawking Zhang <Hawking.Zhang@amd.com> -Date: Sat, 27 May 2017 14:13:51 +0800 -Subject: [PATCH 35/39] tests/amdgpu: bypass UVD ENC tests on raven - -raven doesn't support UVD encode - -Change-Id: Ib880f767ead72b8c7f392c20c01b756600c5eee7 -Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> -Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> ---- - tests/amdgpu/uvd_enc_tests.c | 14 ++++++-------- - 1 file changed, 6 insertions(+), 8 deletions(-) - -diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c -index fee0112..f976443 100644 ---- a/tests/amdgpu/uvd_enc_tests.c -+++ b/tests/amdgpu/uvd_enc_tests.c -@@ -98,10 +98,8 @@ int suite_uvd_enc_tests_init(void) - - family_id = device_handle->info.family_id; - -- if (family_id < AMDGPU_FAMILY_AI) { -- -+ if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) { - printf("\n\nThe ASIC NOT support UVD ENC, all sub-tests will pass\n"); -- - return CUE_SUCCESS; - } - -@@ -123,7 +121,7 @@ int suite_uvd_enc_tests_clean(void) - { - int r; - -- if (family_id < AMDGPU_FAMILY_AI) { -+ if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) { - - r = amdgpu_device_deinitialize(device_handle); - if (r) -@@ -244,7 +242,7 @@ static void amdgpu_cs_uvd_enc_create(void) - { - int len, r; - -- if (family_id < AMDGPU_FAMILY_AI) -+ if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) - return; - - enc.width = 160; -@@ -301,7 +299,7 @@ static void amdgpu_cs_uvd_enc_session_init(void) - { - int len, r; - -- if (family_id < AMDGPU_FAMILY_AI) -+ if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) - return; - - num_resources = 0; -@@ -372,7 +370,7 @@ static void amdgpu_cs_uvd_enc_encode(void) - vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; - cpb_size = vbuf_size * 10; - -- if (family_id < AMDGPU_FAMILY_AI) -+ if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) - return; - - num_resources = 0; -@@ -478,7 +476,7 @@ static void amdgpu_cs_uvd_enc_destroy(void) - struct amdgpu_uvd_enc_bo sw_ctx; - int len, r; - -- if (family_id < AMDGPU_FAMILY_AI) -+ if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) - return; - - num_resources = 0; --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0036-tests-amdgpu-bypass-VCE-tests-on-raven.patch b/meta-v1000/recipes-graphics/drm/libdrm/0036-tests-amdgpu-bypass-VCE-tests-on-raven.patch deleted file mode 100644 index 860c842b..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0036-tests-amdgpu-bypass-VCE-tests-on-raven.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 3e67d0660c38c0fc71287e92fc47ea228294e09f Mon Sep 17 00:00:00 2001 -From: Hawking Zhang <Hawking.Zhang@amd.com> -Date: Sat, 27 May 2017 14:49:19 +0800 -Subject: [PATCH 36/39] tests/amdgpu: bypass VCE tests on raven - -raven doesn't support VCE - -Change-Id: I5f511cd0ca4bcd8114eba16bc35892385453f98b -Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> -Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> ---- - tests/amdgpu/vce_tests.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - -diff --git a/tests/amdgpu/vce_tests.c b/tests/amdgpu/vce_tests.c -index b03807b..8d61a3b 100644 ---- a/tests/amdgpu/vce_tests.c -+++ b/tests/amdgpu/vce_tests.c -@@ -106,6 +106,11 @@ int suite_vce_tests_init(void) - family_id = device_handle->info.family_id; - vce_harvest_config = device_handle->info.vce_harvest_config; - -+ if (family_id >= AMDGPU_FAMILY_RV) { -+ printf("\n\nThe ASIC NOT support VCE, all sub-tests will pass\n"); -+ return CUE_SUCCESS; -+ } -+ - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - if (r) - return CUE_SINIT_FAILED; -@@ -126,6 +131,9 @@ int suite_vce_tests_clean(void) - { - int r; - -+ if (family_id >= AMDGPU_FAMILY_RV) -+ return CUE_SUCCESS; -+ - r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, - ib_mc_address, IB_SIZE); - if (r) -@@ -237,6 +245,9 @@ static void amdgpu_cs_vce_create(void) - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - int len, r; - -+ if (family_id >= AMDGPU_FAMILY_RV) -+ return; -+ - enc.width = vce_create[6]; - enc.height = vce_create[7]; - -@@ -430,6 +441,9 @@ static void amdgpu_cs_vce_encode(void) - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - int i, r; - -+ if (family_id >= AMDGPU_FAMILY_RV) -+ return; -+ - vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; - cpb_size = vbuf_size * 10; - num_resources = 0; -@@ -508,6 +522,9 @@ static void amdgpu_cs_vce_destroy(void) - { - int len, r; - -+ if (family_id >= AMDGPU_FAMILY_RV) -+ return; -+ - num_resources = 0; - alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = enc.fb[0].handle; --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0037-tests-amdgpu-HYBRID-add-SSG-unit-test.patch b/meta-v1000/recipes-graphics/drm/libdrm/0037-tests-amdgpu-HYBRID-add-SSG-unit-test.patch index b9c2a334..77db36a1 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0037-tests-amdgpu-HYBRID-add-SSG-unit-test.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0037-tests-amdgpu-HYBRID-add-SSG-unit-test.patch @@ -7,12 +7,13 @@ Change-Id: I75c5a189a5046b0f56808a60da2f3b34f45e5dab Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- tests/amdgpu/bo_tests.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c -index 930a073..52c9fae 100644 +index 58a00ec..8a7baed 100644 --- a/tests/amdgpu/bo_tests.c +++ b/tests/amdgpu/bo_tests.c @@ -27,6 +27,9 @@ @@ -25,27 +26,26 @@ index 930a073..52c9fae 100644 #include "CUnit/Basic.h" -@@ -49,6 +52,7 @@ static void amdgpu_bo_metadata(void); - static void amdgpu_bo_map_unmap(void); +@@ -51,6 +54,7 @@ static void amdgpu_memory_alloc(void); + static void amdgpu_mem_fail_alloc(void); static void amdgpu_get_fb_id_and_handle(void); static void amdgpu_bo_direct_gma(void); +static void amdgpu_bo_ssg(void); CU_TestInfo bo_tests[] = { { "Export/Import", amdgpu_bo_export_import }, -@@ -58,6 +62,7 @@ CU_TestInfo bo_tests[] = { - { "CPU map/unmap", amdgpu_bo_map_unmap }, +@@ -60,6 +64,7 @@ CU_TestInfo bo_tests[] = { + { "Memory fail alloc Test", amdgpu_mem_fail_alloc }, { "GET FB_ID AND FB_HANDLE", amdgpu_get_fb_id_and_handle }, { "Direct GMA", amdgpu_bo_direct_gma }, + { "SSG", amdgpu_bo_ssg }, CU_TEST_INFO_NULL, }; -@@ -279,3 +284,105 @@ static void amdgpu_bo_direct_gma(void) - } +@@ -282,6 +287,108 @@ static void amdgpu_bo_direct_gma(void) } } -+ + +static void amdgpu_bo_ssg(void) +{ + struct drm_amdgpu_capability cap; @@ -147,6 +147,9 @@ index 930a073..52c9fae 100644 + + amdgpu_bo_free(buf_handle); +} ++ + static void amdgpu_memory_alloc(void) + { + amdgpu_bo_handle bo; -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0038-amdgpu-Add-gpu-always-on-cu-bitmap.patch b/meta-v1000/recipes-graphics/drm/libdrm/0038-amdgpu-Add-gpu-always-on-cu-bitmap.patch deleted file mode 100644 index 19657f5b..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0038-amdgpu-Add-gpu-always-on-cu-bitmap.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 23eabb22a441292a989a6d60bf806b9a655659f2 Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Wed, 28 Jun 2017 13:31:57 +0800 -Subject: [PATCH 38/39] amdgpu: Add gpu always on cu bitmap -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: I8353678c3f74e71af4928dc863b41c92d4dff2ab -Signed-off-by: Flora Cui <Flora.Cui@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - include/drm/amdgpu_drm.h | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 8ced57d..8881a4e 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -842,6 +842,7 @@ struct drm_amdgpu_info_device { - __u64 max_memory_clock; - /* cu information */ - __u32 cu_active_number; -+ /* NOTE: cu_ao_mask is INVALID, DON'T use it */ - __u32 cu_ao_mask; - __u32 cu_bitmap[4][4]; - /** Render backend pipe mask. One render backend is CB+DB. */ -@@ -896,6 +897,8 @@ struct drm_amdgpu_info_device { - /* max gs wavefront per vgt*/ - __u32 max_gs_waves_per_vgt; - __u32 _pad1; -+ /* always on cu bitmap */ -+ __u32 cu_ao_bitmap[4][4]; - }; - - struct drm_amdgpu_info_hw_ip { --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0039-test-amdgpu-fix-test-failure-for-SI.patch b/meta-v1000/recipes-graphics/drm/libdrm/0039-test-amdgpu-fix-test-failure-for-SI.patch deleted file mode 100644 index 0d2872b9..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0039-test-amdgpu-fix-test-failure-for-SI.patch +++ /dev/null @@ -1,675 +0,0 @@ -From 66f95d615faca3ce857e59e3c06ee9469be942a8 Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Wed, 19 Jul 2017 10:52:33 +0800 -Subject: [PATCH 39/39] test/amdgpu: fix test failure for SI - -Change-Id: I646f1bf844bd92962b9f71aa287f90173ae233c6 -Signed-off-by: Flora Cui <Flora.Cui@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - tests/amdgpu/basic_tests.c | 273 ++++++++++++++++++++++++++++++--------------- - tests/amdgpu/cs_tests.c | 41 +++---- - tests/amdgpu/vce_tests.c | 41 +++---- - 3 files changed, 229 insertions(+), 126 deletions(-) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 1807538..c767f7e 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -40,6 +40,7 @@ - static amdgpu_device_handle device_handle; - static uint32_t major_version; - static uint32_t minor_version; -+static uint32_t family_id; - - static void amdgpu_query_info_test(void); - static void amdgpu_memory_alloc(void); -@@ -206,22 +207,56 @@ CU_TestInfo basic_tests[] = { - # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) - # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) - -+#define SDMA_PACKET_SI(op, b, t, s, cnt) ((((op) & 0xF) << 28) | \ -+ (((b) & 0x1) << 26) | \ -+ (((t) & 0x1) << 23) | \ -+ (((s) & 0x1) << 22) | \ -+ (((cnt) & 0xFFFFF) << 0)) -+#define SDMA_OPCODE_COPY_SI 3 -+#define SDMA_OPCODE_CONSTANT_FILL_SI 13 -+#define SDMA_NOP_SI 0xf -+#define GFX_COMPUTE_NOP_SI 0x80000000 -+#define PACKET3_DMA_DATA_SI 0x41 -+# define PACKET3_DMA_DATA_SI_ENGINE(x) ((x) << 27) -+ /* 0 - ME -+ * 1 - PFP -+ */ -+# define PACKET3_DMA_DATA_SI_DST_SEL(x) ((x) << 20) -+ /* 0 - DST_ADDR using DAS -+ * 1 - GDS -+ * 3 - DST_ADDR using L2 -+ */ -+# define PACKET3_DMA_DATA_SI_SRC_SEL(x) ((x) << 29) -+ /* 0 - SRC_ADDR using SAS -+ * 1 - GDS -+ * 2 - DATA -+ * 3 - SRC_ADDR using L2 -+ */ -+# define PACKET3_DMA_DATA_SI_CP_SYNC (1 << 31) -+ - int suite_basic_tests_init(void) - { -+ struct amdgpu_gpu_info gpu_info = {0}; - int r; - - r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle); - -- if (r == 0) -- return CUE_SUCCESS; -- else { -+ if (r) { - if ((r == -EACCES) && (errno == EACCES)) - printf("\n\nError:%s. " - "Hint:Try to run this test program as root.", - strerror(errno)); - return CUE_SINIT_FAILED; - } -+ -+ r = amdgpu_query_gpu_info(device_handle, &gpu_info); -+ if (r) -+ return CUE_SINIT_FAILED; -+ -+ family_id = gpu_info.family_id; -+ -+ return CUE_SUCCESS; - } - - int suite_basic_tests_clean(void) -@@ -308,7 +343,7 @@ static void amdgpu_command_submission_gfx_separate_ibs(void) - uint32_t expired; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle, va_handle_ce; -- int r; -+ int r, i = 0; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); -@@ -333,12 +368,14 @@ static void amdgpu_command_submission_gfx_separate_ibs(void) - - /* IT_SET_CE_DE_COUNTERS */ - ptr = ib_result_ce_cpu; -- ptr[0] = 0xc0008900; -- ptr[1] = 0; -- ptr[2] = 0xc0008400; -- ptr[3] = 1; -+ if (family_id != AMDGPU_FAMILY_SI) { -+ ptr[i++] = 0xc0008900; -+ ptr[i++] = 0; -+ } -+ ptr[i++] = 0xc0008400; -+ ptr[i++] = 1; - ib_info[0].ib_mc_address = ib_result_ce_mc_address; -- ib_info[0].size = 4; -+ ib_info[0].size = i; - ib_info[0].flags = AMDGPU_IB_FLAG_CE; - - /* IT_WAIT_ON_CE_COUNTER */ -@@ -397,7 +434,7 @@ static void amdgpu_command_submission_gfx_shared_ib(void) - uint32_t expired; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle; -- int r; -+ int r, i = 0; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); -@@ -416,12 +453,14 @@ static void amdgpu_command_submission_gfx_shared_ib(void) - - /* IT_SET_CE_DE_COUNTERS */ - ptr = ib_result_cpu; -- ptr[0] = 0xc0008900; -- ptr[1] = 0; -- ptr[2] = 0xc0008400; -- ptr[3] = 1; -+ if (family_id != AMDGPU_FAMILY_SI) { -+ ptr[i++] = 0xc0008900; -+ ptr[i++] = 0; -+ } -+ ptr[i++] = 0xc0008400; -+ ptr[i++] = 1; - ib_info[0].ib_mc_address = ib_result_mc_address; -- ib_info[0].size = 4; -+ ib_info[0].size = i; - ib_info[0].flags = AMDGPU_IB_FLAG_CE; - - ptr = (uint32_t *)ib_result_cpu + 4; -@@ -502,12 +541,21 @@ static void amdgpu_semaphore_test(void) - struct amdgpu_cs_fence fence_status = {0}; - uint32_t *ptr; - uint32_t expired; -+ uint32_t sdma_nop, gfx_nop; - amdgpu_bo_list_handle bo_list[2]; - amdgpu_va_handle va_handle[2]; - amdgpu_sem_handle sem_handle, sem_handle_import; - int fd; - int r, i; - -+ if (family_id == AMDGPU_FAMILY_SI) { -+ sdma_nop = SDMA_PACKET_SI(SDMA_NOP_SI, 0, 0, 0, 0); -+ gfx_nop = GFX_COMPUTE_NOP_SI; -+ } else { -+ sdma_nop = SDMA_PKT_HEADER_OP(SDMA_NOP); -+ gfx_nop = GFX_COMPUTE_NOP; -+ } -+ - r = amdgpu_cs_create_semaphore(&sem); - CU_ASSERT_EQUAL(r, 0); - for (i = 0; i < 2; i++) { -@@ -527,7 +575,7 @@ static void amdgpu_semaphore_test(void) - - /* 1. same context different engine */ - ptr = ib_result_cpu[0]; -- ptr[0] = SDMA_NOP; -+ ptr[0] = sdma_nop; - ib_info[0].ib_mc_address = ib_result_mc_address[0]; - ib_info[0].size = 1; - -@@ -544,7 +592,7 @@ static void amdgpu_semaphore_test(void) - r = amdgpu_cs_wait_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem); - CU_ASSERT_EQUAL(r, 0); - ptr = ib_result_cpu[1]; -- ptr[0] = GFX_COMPUTE_NOP; -+ ptr[0] = gfx_nop; - ib_info[1].ib_mc_address = ib_result_mc_address[1]; - ib_info[1].size = 1; - -@@ -568,7 +616,7 @@ static void amdgpu_semaphore_test(void) - - /* 2. same engine different context */ - ptr = ib_result_cpu[0]; -- ptr[0] = GFX_COMPUTE_NOP; -+ ptr[0] = gfx_nop; - ib_info[0].ib_mc_address = ib_result_mc_address[0]; - ib_info[0].size = 1; - -@@ -585,7 +633,7 @@ static void amdgpu_semaphore_test(void) - r = amdgpu_cs_wait_semaphore(context_handle[1], AMDGPU_HW_IP_GFX, 0, 0, sem); - CU_ASSERT_EQUAL(r, 0); - ptr = ib_result_cpu[1]; -- ptr[0] = GFX_COMPUTE_NOP; -+ ptr[0] = gfx_nop; - ib_info[1].ib_mc_address = ib_result_mc_address[1]; - ib_info[1].size = 1; - -@@ -612,7 +660,7 @@ static void amdgpu_semaphore_test(void) - CU_ASSERT_EQUAL(r, 0); - - ptr = ib_result_cpu[0]; -- ptr[0] = SDMA_NOP; -+ ptr[0] = sdma_nop; - ib_info[0].ib_mc_address = ib_result_mc_address[0]; - ib_info[0].size = 1; - -@@ -639,7 +687,7 @@ static void amdgpu_semaphore_test(void) - r = amdgpu_cs_wait_sem(device_handle, context_handle[1], AMDGPU_HW_IP_GFX, 0, 0, sem_handle_import); - CU_ASSERT_EQUAL(r, 0); - ptr = ib_result_cpu[1]; -- ptr[0] = GFX_COMPUTE_NOP; -+ ptr[0] = gfx_nop; - ib_info[1].ib_mc_address = ib_result_mc_address[1]; - ib_info[1].size = 1; - -@@ -694,11 +742,15 @@ static void amdgpu_command_submission_compute_nop(void) - int i, r, instance; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle; -+ struct drm_amdgpu_info_hw_ip info; -+ -+ r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_COMPUTE, 0, &info); -+ CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - -- for (instance = 0; instance < 8; instance++) { -+ for (instance = 0; (1 << instance) & info.available_rings; instance++) { - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle, &ib_result_cpu, -@@ -710,8 +762,8 @@ static void amdgpu_command_submission_compute_nop(void) - CU_ASSERT_EQUAL(r, 0); - - ptr = ib_result_cpu; -- for (i = 0; i < 16; ++i) -- ptr[i] = 0xffff1000; -+ memset(ptr, 0, 16); -+ ptr[0]=PACKET3(PACKET3_NOP, 14); - - memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); - ib_info.ib_mc_address = ib_result_mc_address; -@@ -872,16 +924,12 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) - uint32_t *pm4; - struct amdgpu_cs_ib_info *ib_info; - struct amdgpu_cs_request *ibs_request; -- struct amdgpu_gpu_info gpu_info = {0}; - uint64_t bo_mc; - volatile uint32_t *bo_cpu; - int i, j, r, loop; - uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; - amdgpu_va_handle va_handle; - -- r = amdgpu_query_gpu_info(device_handle, &gpu_info); -- CU_ASSERT_EQUAL(r, 0); -- - pm4 = calloc(pm4_dw, sizeof(*pm4)); - CU_ASSERT_NOT_EQUAL(pm4, NULL); - -@@ -917,13 +965,17 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) - /* fulfill PM4: test DMA write-linear */ - i = j = 0; - if (ip_type == AMDGPU_HW_IP_DMA) { -- pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, -- SDMA_WRITE_SUB_OPCODE_LINEAR, 0); -+ if (family_id == AMDGPU_FAMILY_SI) -+ pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0, -+ sdma_write_length); -+ else -+ pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, -+ SDMA_WRITE_SUB_OPCODE_LINEAR, 0); - pm4[i++] = 0xffffffff & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; -- if (gpu_info.family_id >= AMDGPU_FAMILY_AI) -+ if (family_id >= AMDGPU_FAMILY_AI) - pm4[i++] = sdma_write_length - 1; -- else -+ else if (family_id != AMDGPU_FAMILY_SI) - pm4[i++] = sdma_write_length; - while(j++ < sdma_write_length) - pm4[i++] = 0xdeadbeaf; -@@ -980,16 +1032,12 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) - uint32_t *pm4; - struct amdgpu_cs_ib_info *ib_info; - struct amdgpu_cs_request *ibs_request; -- struct amdgpu_gpu_info gpu_info = {0}; - uint64_t bo_mc; - volatile uint32_t *bo_cpu; - int i, j, r, loop; - uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; - amdgpu_va_handle va_handle; - -- r = amdgpu_query_gpu_info(device_handle, &gpu_info); -- CU_ASSERT_EQUAL(r, 0); -- - pm4 = calloc(pm4_dw, sizeof(*pm4)); - CU_ASSERT_NOT_EQUAL(pm4, NULL); - -@@ -1024,27 +1072,47 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) - /* fulfill PM4: test DMA const fill */ - i = j = 0; - if (ip_type == AMDGPU_HW_IP_DMA) { -- pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, -- SDMA_CONSTANT_FILL_EXTRA_SIZE(2)); -- pm4[i++] = 0xffffffff & bo_mc; -- pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; -- pm4[i++] = 0xdeadbeaf; -- if (gpu_info.family_id >= AMDGPU_FAMILY_AI) -- pm4[i++] = sdma_write_length - 1; -- else -- pm4[i++] = sdma_write_length; -+ if (family_id == AMDGPU_FAMILY_SI) { -+ pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_CONSTANT_FILL_SI, 0, 0, 0, -+ sdma_write_length / 4); -+ pm4[i++] = 0xfffffffc & bo_mc; -+ pm4[i++] = 0xdeadbeaf; -+ pm4[i++] = (0xffffffff00000000 & bo_mc) >> 16; -+ } else { -+ pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, -+ SDMA_CONSTANT_FILL_EXTRA_SIZE(2)); -+ pm4[i++] = 0xffffffff & bo_mc; -+ pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; -+ pm4[i++] = 0xdeadbeaf; -+ if (family_id >= AMDGPU_FAMILY_AI) -+ pm4[i++] = sdma_write_length - 1; -+ else -+ pm4[i++] = sdma_write_length; -+ } - } else if ((ip_type == AMDGPU_HW_IP_GFX) || - (ip_type == AMDGPU_HW_IP_COMPUTE)) { -- pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); -- pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | -- PACKET3_DMA_DATA_DST_SEL(0) | -- PACKET3_DMA_DATA_SRC_SEL(2) | -- PACKET3_DMA_DATA_CP_SYNC; -- pm4[i++] = 0xdeadbeaf; -- pm4[i++] = 0; -- pm4[i++] = 0xfffffffc & bo_mc; -- pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; -- pm4[i++] = sdma_write_length; -+ if (family_id == AMDGPU_FAMILY_SI) { -+ pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4); -+ pm4[i++] = 0xdeadbeaf; -+ pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) | -+ PACKET3_DMA_DATA_SI_DST_SEL(0) | -+ PACKET3_DMA_DATA_SI_SRC_SEL(2) | -+ PACKET3_DMA_DATA_SI_CP_SYNC; -+ pm4[i++] = 0xffffffff & bo_mc; -+ pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; -+ pm4[i++] = sdma_write_length; -+ } else { -+ pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); -+ pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | -+ PACKET3_DMA_DATA_DST_SEL(0) | -+ PACKET3_DMA_DATA_SRC_SEL(2) | -+ PACKET3_DMA_DATA_CP_SYNC; -+ pm4[i++] = 0xdeadbeaf; -+ pm4[i++] = 0; -+ pm4[i++] = 0xfffffffc & bo_mc; -+ pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; -+ pm4[i++] = sdma_write_length; -+ } - } - - amdgpu_test_exec_cs_helper(context_handle, -@@ -1090,16 +1158,12 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) - uint32_t *pm4; - struct amdgpu_cs_ib_info *ib_info; - struct amdgpu_cs_request *ibs_request; -- struct amdgpu_gpu_info gpu_info = {0}; - uint64_t bo1_mc, bo2_mc; - volatile unsigned char *bo1_cpu, *bo2_cpu; - int i, j, r, loop1, loop2; - uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; - amdgpu_va_handle bo1_va_handle, bo2_va_handle; - -- r = amdgpu_query_gpu_info(device_handle, &gpu_info); -- CU_ASSERT_EQUAL(r, 0); -- - pm4 = calloc(pm4_dw, sizeof(*pm4)); - CU_ASSERT_NOT_EQUAL(pm4, NULL); - -@@ -1150,28 +1214,51 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) - /* fulfill PM4: test DMA copy linear */ - i = j = 0; - if (ip_type == AMDGPU_HW_IP_DMA) { -- pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); -- if (gpu_info.family_id >= AMDGPU_FAMILY_AI) -- pm4[i++] = sdma_write_length - 1; -- else -- pm4[i++] = sdma_write_length; -- pm4[i++] = 0; -- pm4[i++] = 0xffffffff & bo1_mc; -- pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; -- pm4[i++] = 0xffffffff & bo2_mc; -- pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; -+ if (family_id == AMDGPU_FAMILY_SI) { -+ pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0, -+ sdma_write_length); -+ pm4[i++] = 0xffffffff & bo2_mc; -+ pm4[i++] = 0xffffffff & bo1_mc; -+ pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; -+ pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; -+ } else { -+ pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); -+ if (family_id >= AMDGPU_FAMILY_AI) -+ pm4[i++] = sdma_write_length - 1; -+ else -+ pm4[i++] = sdma_write_length; -+ pm4[i++] = 0; -+ pm4[i++] = 0xffffffff & bo1_mc; -+ pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; -+ pm4[i++] = 0xffffffff & bo2_mc; -+ pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; -+ } -+ - } else if ((ip_type == AMDGPU_HW_IP_GFX) || - (ip_type == AMDGPU_HW_IP_COMPUTE)) { -- pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); -- pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | -- PACKET3_DMA_DATA_DST_SEL(0) | -- PACKET3_DMA_DATA_SRC_SEL(0) | -- PACKET3_DMA_DATA_CP_SYNC; -- pm4[i++] = 0xfffffffc & bo1_mc; -- pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; -- pm4[i++] = 0xfffffffc & bo2_mc; -- pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; -- pm4[i++] = sdma_write_length; -+ if (family_id == AMDGPU_FAMILY_SI) { -+ pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4); -+ pm4[i++] = 0xfffffffc & bo1_mc; -+ pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) | -+ PACKET3_DMA_DATA_SI_DST_SEL(0) | -+ PACKET3_DMA_DATA_SI_SRC_SEL(0) | -+ PACKET3_DMA_DATA_SI_CP_SYNC | -+ (0xffff00000000 & bo1_mc) >> 32; -+ pm4[i++] = 0xfffffffc & bo2_mc; -+ pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; -+ pm4[i++] = sdma_write_length; -+ } else { -+ pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); -+ pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | -+ PACKET3_DMA_DATA_DST_SEL(0) | -+ PACKET3_DMA_DATA_SRC_SEL(0) | -+ PACKET3_DMA_DATA_CP_SYNC; -+ pm4[i++] = 0xfffffffc & bo1_mc; -+ pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; -+ pm4[i++] = 0xfffffffc & bo2_mc; -+ pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; -+ pm4[i++] = sdma_write_length; -+ } - } - - amdgpu_test_exec_cs_helper(context_handle, -@@ -1232,7 +1319,7 @@ static void amdgpu_command_submission_multi_fence_wait_all(bool wait_all) - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle, va_handle_ce; - int r; -- int i, ib_cs_num = 2; -+ int i = 0, ib_cs_num = 2; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); -@@ -1257,12 +1344,14 @@ static void amdgpu_command_submission_multi_fence_wait_all(bool wait_all) - - /* IT_SET_CE_DE_COUNTERS */ - ptr = ib_result_ce_cpu; -- ptr[0] = 0xc0008900; -- ptr[1] = 0; -- ptr[2] = 0xc0008400; -- ptr[3] = 1; -+ if (family_id != AMDGPU_FAMILY_SI) { -+ ptr[i++] = 0xc0008900; -+ ptr[i++] = 0; -+ } -+ ptr[i++] = 0xc0008400; -+ ptr[i++] = 1; - ib_info[0].ib_mc_address = ib_result_ce_mc_address; -- ib_info[0].size = 4; -+ ib_info[0].size = i; - ib_info[0].flags = AMDGPU_IB_FLAG_CE; - - /* IT_WAIT_ON_CE_COUNTER */ -@@ -1363,11 +1452,19 @@ static void amdgpu_userptr_test(void) - handle = buf_handle; - - j = i = 0; -- pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, -- SDMA_WRITE_SUB_OPCODE_LINEAR, 0); -+ -+ if (family_id == AMDGPU_FAMILY_SI) -+ pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0, -+ sdma_write_length); -+ else -+ pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, -+ SDMA_WRITE_SUB_OPCODE_LINEAR, 0); - pm4[i++] = 0xffffffff & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; -- pm4[i++] = sdma_write_length; -+ if (family_id >= AMDGPU_FAMILY_AI) -+ pm4[i++] = sdma_write_length - 1; -+ else if (family_id != AMDGPU_FAMILY_SI) -+ pm4[i++] = sdma_write_length; - - while (j++ < sdma_write_length) - pm4[i++] = 0xdeadbeaf; -diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c -index df55c70..3b2f17d 100644 ---- a/tests/amdgpu/cs_tests.c -+++ b/tests/amdgpu/cs_tests.c -@@ -90,7 +90,7 @@ int suite_cs_tests_init(void) - chip_rev = device_handle->info.chip_rev; - chip_id = device_handle->info.chip_external_rev; - -- if (family_id >= AMDGPU_FAMILY_RV) { -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { - printf("\n\nThe ASIC NOT support UVD, all sub-tests will pass\n"); - return CUE_SUCCESS; - } -@@ -119,21 +119,24 @@ int suite_cs_tests_clean(void) - { - int r; - -- if (family_id >= AMDGPU_FAMILY_RV) -- return CUE_SUCCESS; -- -- r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, -- ib_mc_address, IB_SIZE); -- if (r) -- return CUE_SCLEAN_FAILED; -- -- r = amdgpu_cs_ctx_free(context_handle); -- if (r) -- return CUE_SCLEAN_FAILED; -- -- r = amdgpu_device_deinitialize(device_handle); -- if (r) -- return CUE_SCLEAN_FAILED; -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { -+ r = amdgpu_device_deinitialize(device_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ } else { -+ r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, -+ ib_mc_address, IB_SIZE); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ -+ r = amdgpu_cs_ctx_free(context_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ -+ r = amdgpu_device_deinitialize(device_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ } - - return CUE_SUCCESS; - } -@@ -200,7 +203,7 @@ static void amdgpu_cs_uvd_create(void) - void *msg; - int i, r; - -- if (family_id >= AMDGPU_FAMILY_RV) -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - - req.alloc_size = 4*1024; -@@ -274,7 +277,7 @@ static void amdgpu_cs_uvd_decode(void) - uint8_t *ptr; - int i, r; - -- if (family_id >= AMDGPU_FAMILY_RV) -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - - req.alloc_size = 4*1024; /* msg */ -@@ -416,7 +419,7 @@ static void amdgpu_cs_uvd_destroy(void) - void *msg; - int i, r; - -- if (family_id >= AMDGPU_FAMILY_RV) -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - - req.alloc_size = 4*1024; -diff --git a/tests/amdgpu/vce_tests.c b/tests/amdgpu/vce_tests.c -index 8d61a3b..cf44c13 100644 ---- a/tests/amdgpu/vce_tests.c -+++ b/tests/amdgpu/vce_tests.c -@@ -106,7 +106,7 @@ int suite_vce_tests_init(void) - family_id = device_handle->info.family_id; - vce_harvest_config = device_handle->info.vce_harvest_config; - -- if (family_id >= AMDGPU_FAMILY_RV) { -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { - printf("\n\nThe ASIC NOT support VCE, all sub-tests will pass\n"); - return CUE_SUCCESS; - } -@@ -131,21 +131,24 @@ int suite_vce_tests_clean(void) - { - int r; - -- if (family_id >= AMDGPU_FAMILY_RV) -- return CUE_SUCCESS; -- -- r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, -- ib_mc_address, IB_SIZE); -- if (r) -- return CUE_SCLEAN_FAILED; -- -- r = amdgpu_cs_ctx_free(context_handle); -- if (r) -- return CUE_SCLEAN_FAILED; -- -- r = amdgpu_device_deinitialize(device_handle); -- if (r) -- return CUE_SCLEAN_FAILED; -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { -+ r = amdgpu_device_deinitialize(device_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ } else { -+ r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, -+ ib_mc_address, IB_SIZE); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ -+ r = amdgpu_cs_ctx_free(context_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ -+ r = amdgpu_device_deinitialize(device_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ } - - return CUE_SUCCESS; - } -@@ -245,7 +248,7 @@ static void amdgpu_cs_vce_create(void) - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - int len, r; - -- if (family_id >= AMDGPU_FAMILY_RV) -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - - enc.width = vce_create[6]; -@@ -441,7 +444,7 @@ static void amdgpu_cs_vce_encode(void) - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - int i, r; - -- if (family_id >= AMDGPU_FAMILY_RV) -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - - vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; -@@ -522,7 +525,7 @@ static void amdgpu_cs_vce_destroy(void) - { - int len, r; - -- if (family_id >= AMDGPU_FAMILY_RV) -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - - num_resources = 0; --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0040-drm-fix-missing-mutex-unlock-before-return.patch b/meta-v1000/recipes-graphics/drm/libdrm/0040-drm-fix-missing-mutex-unlock-before-return.patch deleted file mode 100644 index 8420eee4..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0040-drm-fix-missing-mutex-unlock-before-return.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 8649ecc02c75f70bcc7bcc38fa2bd55da43c86f3 Mon Sep 17 00:00:00 2001 -From: Monk Liu <monk.liu@amd.com> -Date: Mon, 7 Aug 2017 22:25:35 +0800 -Subject: [PATCH 40/46] drm: fix missing mutex unlock before return -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: I377dde976648d53bc9a3a2d5ba294c284910b109 -Signed-off-by: Monk Liu <monk.liu@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> -Acked-by: Qiang Yu <Qiang.Yu@amd.com> ---- - amdgpu/amdgpu_bo.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 9534c40..76126a2 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -304,6 +304,7 @@ int amdgpu_bo_import(amdgpu_device_handle dev, - /* Get a KMS handle. */ - r = drmPrimeFDToHandle(dev->fd, shared_handle, &handle); - if (r) { -+ pthread_mutex_unlock(&dev->bo_table_mutex); - return r; - } - --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0041-drm-fix-race-issue-between-two-bo-functions-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0041-drm-fix-race-issue-between-two-bo-functions-v2.patch deleted file mode 100644 index 26d8af22..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0041-drm-fix-race-issue-between-two-bo-functions-v2.patch +++ /dev/null @@ -1,83 +0,0 @@ -From ce2f6104799cca43993e831c889ded27af877a25 Mon Sep 17 00:00:00 2001 -From: Monk Liu <monk.liu@amd.com> -Date: Mon, 7 Aug 2017 22:27:10 +0800 -Subject: [PATCH 41/46] drm:fix race issue between two bo functions(v2) -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -there is race issue between two threads on amdgpu_bo_reference and -amdgpu_bo_import, this patch tends to fix it by moving the -pthread_mutex_lock out of bo_free_internal and move to bo_reference -to cover the update_reference part. - -The mutex_unlock in bo_import should also cover bo refcount -increasement. - -Change-Id: I1f65eacf74cd28cc0d3a71ef2f7a19b890d63c29 -Signed-off-by: Monk Liu <monk.liu@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> -Acked-by: Qiang Yu <Qiang.Yu@amd.com> ---- - amdgpu/amdgpu_bo.c | 5 +---- - amdgpu/amdgpu_internal.h | 13 +++++++++++-- - 2 files changed, 12 insertions(+), 6 deletions(-) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 76126a2..09028c7 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -57,14 +57,12 @@ static void amdgpu_close_kms_handle(amdgpu_device_handle dev, - drm_private void amdgpu_bo_free_internal(amdgpu_bo_handle bo) - { - /* Remove the buffer from the hash tables. */ -- pthread_mutex_lock(&bo->dev->bo_table_mutex); - util_hash_table_remove(bo->dev->bo_handles, - (void*)(uintptr_t)bo->handle); - if (bo->flink_name) { - util_hash_table_remove(bo->dev->bo_flink_names, - (void*)(uintptr_t)bo->flink_name); - } -- pthread_mutex_unlock(&bo->dev->bo_table_mutex); - - /* Release CPU access. */ - if (bo->cpu_map_count > 0) { -@@ -344,10 +342,9 @@ int amdgpu_bo_import(amdgpu_device_handle dev, - } - - if (bo) { -- pthread_mutex_unlock(&dev->bo_table_mutex); -- - /* The buffer already exists, just bump the refcount. */ - atomic_inc(&bo->refcount); -+ pthread_mutex_unlock(&dev->bo_table_mutex); - - output->buf_handle = bo; - output->alloc_size = bo->alloc_size; -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index b39f47a..d7a3d50 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -238,8 +238,17 @@ static inline bool update_references(atomic_t *dst, atomic_t *src) - static inline void amdgpu_bo_reference(struct amdgpu_bo **dst, - struct amdgpu_bo *src) - { -- if (update_references(&(*dst)->refcount, &src->refcount)) -- amdgpu_bo_free_internal(*dst); -+ pthread_mutex_t *mlock; -+ struct amdgpu_bo* bo = *dst; -+ -+ assert(bo != NULL); -+ mlock = &bo->dev->bo_table_mutex; -+ pthread_mutex_lock(mlock); -+ -+ if (update_references(&bo->refcount, src ? &src->refcount : NULL)) -+ amdgpu_bo_free_internal(bo); -+ -+ pthread_mutex_unlock(mlock); - *dst = src; - } - --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0042-amdgpu-fix-potential-deadlock.patch b/meta-v1000/recipes-graphics/drm/libdrm/0042-amdgpu-fix-potential-deadlock.patch deleted file mode 100644 index 0f8ba2f9..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0042-amdgpu-fix-potential-deadlock.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 9f8b9e8733f123afd7589314cdb6afc9944b19ae Mon Sep 17 00:00:00 2001 -From: Monk Liu <Monk.Liu@amd.com> -Date: Tue, 8 Aug 2017 16:16:29 +0800 -Subject: [PATCH 42/46] amdgpu:fix potential deadlock - -deadlock could occure between cpu mutex lock and -bo table mutex lock, this patch avoid it. - -Change-Id: I083e402dde48f02a8ee196e59aa0cab80849fc18 -Signed-off-by: Monk Liu <Monk.Liu@amd.com> -Acked-by: Qiang Yu <Qiang.Yu@amd.com> ---- - amdgpu/amdgpu_bo.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 09028c7..c973a0d 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -673,10 +673,10 @@ int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu) - pthread_mutex_unlock(&bo->cpu_access_mutex); - return -errno; - } -- amdgpu_add_handle_to_table(bo); - bo->cpu_ptr = ptr; - bo->cpu_map_count = 1; - pthread_mutex_unlock(&bo->cpu_access_mutex); -+ amdgpu_add_handle_to_table(bo); - - *cpu = ptr; - return 0; --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0043-Revert-amdgpu-fix-potential-deadlock.patch b/meta-v1000/recipes-graphics/drm/libdrm/0043-Revert-amdgpu-fix-potential-deadlock.patch deleted file mode 100644 index 1048cf31..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0043-Revert-amdgpu-fix-potential-deadlock.patch +++ /dev/null @@ -1,33 +0,0 @@ -From b470ecceb52b526260b0e34ee0017332a77b283c Mon Sep 17 00:00:00 2001 -From: Qiang Yu <Qiang.Yu@amd.com> -Date: Thu, 10 Aug 2017 15:13:07 +0800 -Subject: [PATCH 43/46] Revert "amdgpu:fix potential deadlock" - -This reverts commit eaea24b7acfb8d2cb1db8baa8f353d9fcc69a2b6. - -The reverted commit is submitted by mistaken. - -Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> ---- - amdgpu/amdgpu_bo.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index c973a0d..09028c7 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -673,10 +673,10 @@ int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu) - pthread_mutex_unlock(&bo->cpu_access_mutex); - return -errno; - } -+ amdgpu_add_handle_to_table(bo); - bo->cpu_ptr = ptr; - bo->cpu_map_count = 1; - pthread_mutex_unlock(&bo->cpu_access_mutex); -- amdgpu_add_handle_to_table(bo); - - *cpu = ptr; - return 0; --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0045-amdgpu-merge-and-cleanup-amdgpu_bo_free.patch b/meta-v1000/recipes-graphics/drm/libdrm/0045-amdgpu-merge-and-cleanup-amdgpu_bo_free.patch deleted file mode 100644 index 60a3b53f..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0045-amdgpu-merge-and-cleanup-amdgpu_bo_free.patch +++ /dev/null @@ -1,143 +0,0 @@ -From 9cdb2d8f7e3a3ea21a677a8c9160c69dc968ad0b Mon Sep 17 00:00:00 2001 -From: Monk Liu <monk.liu@amd.com> -Date: Tue, 8 Aug 2017 12:09:07 -0400 -Subject: [PATCH 45/46] amdgpu: merge and cleanup amdgpu_bo_free -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -since bo_reference and bo_internal_free are -all only used by bo_free, so we just merge them -together - -Change-Id: I01355e7d450b075458b946717d5bddfa0a0c2d3c -Reviewed-by: Christian König <christian.koenig@amd.com> -Signed-off-by: Monk Liu <monk.liu@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - amdgpu/amdgpu_bo.c | 52 +++++++++++++++++++++++++++--------------------- - amdgpu/amdgpu_internal.h | 33 ------------------------------ - 2 files changed, 29 insertions(+), 56 deletions(-) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 1d90e5e..57aaf97 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -54,27 +54,6 @@ static void amdgpu_close_kms_handle(amdgpu_device_handle dev, - drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, &args); - } - --drm_private void amdgpu_bo_free_internal(amdgpu_bo_handle bo) --{ -- /* Remove the buffer from the hash tables. */ -- util_hash_table_remove(bo->dev->bo_handles, -- (void*)(uintptr_t)bo->handle); -- if (bo->flink_name) { -- util_hash_table_remove(bo->dev->bo_flink_names, -- (void*)(uintptr_t)bo->flink_name); -- } -- -- /* Release CPU access. */ -- if (bo->cpu_map_count > 0) { -- bo->cpu_map_count = 1; -- amdgpu_bo_cpu_unmap(bo); -- } -- -- amdgpu_close_kms_handle(bo->dev, bo->handle); -- pthread_mutex_destroy(&bo->cpu_access_mutex); -- free(bo); --} -- - int amdgpu_bo_alloc(amdgpu_device_handle dev, - struct amdgpu_bo_alloc_request *alloc_buffer, - amdgpu_bo_handle *buf_handle) -@@ -623,8 +602,35 @@ int amdgpu_bo_get_phys_address(amdgpu_bo_handle buf_handle, - - int amdgpu_bo_free(amdgpu_bo_handle buf_handle) - { -- /* Just drop the reference. */ -- amdgpu_bo_reference(&buf_handle, NULL); -+ struct amdgpu_device *dev; -+ struct amdgpu_bo *bo = buf_handle; -+ -+ assert(bo != NULL); -+ dev = bo->dev; -+ pthread_mutex_lock(&dev->bo_table_mutex); -+ -+ if (update_references(&bo->refcount, NULL)) { -+ /* Remove the buffer from the hash tables. */ -+ util_hash_table_remove(dev->bo_handles, -+ (void*)(uintptr_t)bo->handle); -+ -+ if (bo->flink_name) { -+ util_hash_table_remove(dev->bo_flink_names, -+ (void*)(uintptr_t)bo->flink_name); -+ } -+ -+ /* Release CPU access. */ -+ if (bo->cpu_map_count > 0) { -+ bo->cpu_map_count = 1; -+ amdgpu_bo_cpu_unmap(bo); -+ } -+ -+ amdgpu_close_kms_handle(dev, bo->handle); -+ pthread_mutex_destroy(&bo->cpu_access_mutex); -+ free(bo); -+ } -+ -+ pthread_mutex_unlock(&dev->bo_table_mutex); - return 0; - } - -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index d7a3d50..fd522f3 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -161,8 +161,6 @@ struct amdgpu_semaphore { - * Functions. - */ - --drm_private void amdgpu_bo_free_internal(amdgpu_bo_handle bo); -- - drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, - uint64_t max, uint64_t alignment); - -@@ -221,35 +219,4 @@ static inline bool update_references(atomic_t *dst, atomic_t *src) - return false; - } - --/** -- * Assignment between two amdgpu_bo pointers with reference counting. -- * -- * Usage: -- * struct amdgpu_bo *dst = ... , *src = ...; -- * -- * dst = src; -- * // No reference counting. Only use this when you need to move -- * // a reference from one pointer to another. -- * -- * amdgpu_bo_reference(&dst, src); -- * // Reference counters are updated. dst is decremented and src is -- * // incremented. dst is freed if its reference counter is 0. -- */ --static inline void amdgpu_bo_reference(struct amdgpu_bo **dst, -- struct amdgpu_bo *src) --{ -- pthread_mutex_t *mlock; -- struct amdgpu_bo* bo = *dst; -- -- assert(bo != NULL); -- mlock = &bo->dev->bo_table_mutex; -- pthread_mutex_lock(mlock); -- -- if (update_references(&bo->refcount, src ? &src->refcount : NULL)) -- amdgpu_bo_free_internal(bo); -- -- pthread_mutex_unlock(mlock); -- *dst = src; --} -- - #endif --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0046-tests-amdgpu-update-uvd-enc-test-for-new-fw.patch b/meta-v1000/recipes-graphics/drm/libdrm/0046-tests-amdgpu-update-uvd-enc-test-for-new-fw.patch deleted file mode 100644 index 41765153..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0046-tests-amdgpu-update-uvd-enc-test-for-new-fw.patch +++ /dev/null @@ -1,765 +0,0 @@ -From 3b1134521e5ca5ad1b5cb5212171b3702b70b886 Mon Sep 17 00:00:00 2001 -From: Boyuan Zhang <boyuan.zhang@amd.com> -Date: Fri, 4 Aug 2017 14:49:13 -0400 -Subject: [PATCH 46/46] tests/amdgpu: update uvd enc test for new fw - -uvd hevc enc test failed due to firmware interface changes. -re-write the test based on the new firmware interface. - -Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> -Acked-by: Alex Deucher <alexander.deucher at amd.com> ---- - tests/amdgpu/uvd_enc_tests.c | 138 ++++++++-------- - tests/amdgpu/uve_ib.h | 378 +++++++++++++++++++++++++++++++++---------- - 2 files changed, 358 insertions(+), 158 deletions(-) - -diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c -index f976443..6c19f7b 100644 ---- a/tests/amdgpu/uvd_enc_tests.c -+++ b/tests/amdgpu/uvd_enc_tests.c -@@ -252,30 +252,12 @@ static void amdgpu_cs_uvd_enc_create(void) - alloc_resource(&enc.session, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = enc.session.handle; - resources[num_resources++] = ib_handle; -- -- len = 0; -- memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); -- len += sizeof(uve_session_info) / 4; -- ib_cpu[len++] = enc.session.addr >> 32; -- ib_cpu[len++] = enc.session.addr; -- -- memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); -- len += sizeof(uve_task_info) / 4; -- ib_cpu[len++] = 0x0000001c; -- ib_cpu[len++] = 0x00000000; -- ib_cpu[len++] = 0x00000000; -- -- memcpy((ib_cpu + len), uve_op_init, sizeof(uve_op_init)); -- len += sizeof(uve_op_init) / 4; -- -- r = submit(len, AMDGPU_HW_IP_UVD_ENC); -- CU_ASSERT_EQUAL(r, 0); - } - - static void check_result(struct amdgpu_uvd_enc *enc) - { - uint64_t sum; -- uint32_t s = 20626; -+ uint32_t s = 26382; - uint32_t *ptr, size; - int i, j, r; - -@@ -302,11 +284,6 @@ static void amdgpu_cs_uvd_enc_session_init(void) - if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) - return; - -- num_resources = 0; -- alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_GTT); -- resources[num_resources++] = enc.fb.handle; -- resources[num_resources++] = ib_handle; -- - len = 0; - memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); - len += sizeof(uve_session_info) / 4; -@@ -315,9 +292,12 @@ static void amdgpu_cs_uvd_enc_session_init(void) - - memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); - len += sizeof(uve_task_info) / 4; -- ib_cpu[len++] = 0x000001c0; -- ib_cpu[len++] = 0x00000001; -- ib_cpu[len++] = 0x00000001; -+ ib_cpu[len++] = 0x000000d8; -+ ib_cpu[len++] = 0x00000000; -+ ib_cpu[len++] = 0x00000000; -+ -+ memcpy((ib_cpu + len), uve_op_init, sizeof(uve_op_init)); -+ len += sizeof(uve_op_init) / 4; - - memcpy((ib_cpu + len), uve_session_init, sizeof(uve_session_init)); - len += sizeof(uve_session_init) / 4; -@@ -325,9 +305,6 @@ static void amdgpu_cs_uvd_enc_session_init(void) - memcpy((ib_cpu + len), uve_layer_ctrl, sizeof(uve_layer_ctrl)); - len += sizeof(uve_layer_ctrl) / 4; - -- memcpy((ib_cpu + len), uve_layer_select, sizeof(uve_layer_select)); -- len += sizeof(uve_layer_select) / 4; -- - memcpy((ib_cpu + len), uve_slice_ctrl, sizeof(uve_slice_ctrl)); - len += sizeof(uve_slice_ctrl) / 4; - -@@ -337,35 +314,27 @@ static void amdgpu_cs_uvd_enc_session_init(void) - memcpy((ib_cpu + len), uve_rc_session_init, sizeof(uve_rc_session_init)); - len += sizeof(uve_rc_session_init) / 4; - -- memcpy((ib_cpu + len), uve_rc_layer_init, sizeof(uve_rc_layer_init)); -- len += sizeof(uve_rc_layer_init) / 4; -- -- memcpy((ib_cpu + len), uve_hw_spec, sizeof(uve_hw_spec)); -- len += sizeof(uve_hw_spec) / 4; -- - memcpy((ib_cpu + len), uve_deblocking_filter, sizeof(uve_deblocking_filter)); - len += sizeof(uve_deblocking_filter) / 4; - -- memcpy((ib_cpu + len), uve_feedback_buffer, sizeof(uve_feedback_buffer)); -- len += sizeof(uve_feedback_buffer) / 4; -- ib_cpu[len++] = enc.fb.addr >> 32; -- ib_cpu[len++] = enc.fb.addr; -- ib_cpu[len++] = 0x00000003; -+ memcpy((ib_cpu + len), uve_quality_params, sizeof(uve_quality_params)); -+ len += sizeof(uve_quality_params) / 4; - - memcpy((ib_cpu + len), uve_op_init_rc, sizeof(uve_op_init_rc)); - len += sizeof(uve_op_init_rc) / 4; - -+ memcpy((ib_cpu + len), uve_op_init_rc_vbv_level, sizeof(uve_op_init_rc_vbv_level)); -+ len += sizeof(uve_op_init_rc_vbv_level) / 4; -+ - r = submit(len, AMDGPU_HW_IP_UVD_ENC); - CU_ASSERT_EQUAL(r, 0); -- -- free_resource(&enc.fb); - } - - static void amdgpu_cs_uvd_enc_encode(void) - { - int len, r, i; - uint64_t luma_offset, chroma_offset; -- uint32_t vbuf_size, bs_size = 0x154000, cpb_size; -+ uint32_t vbuf_size, bs_size = 0x003f4800, cpb_size; - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; - cpb_size = vbuf_size * 10; -@@ -408,55 +377,82 @@ static void amdgpu_cs_uvd_enc_encode(void) - - memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); - len += sizeof(uve_task_info) / 4; -- ib_cpu[len++] = 0x00000210; -- ib_cpu[len++] = 0x00000002; -+ ib_cpu[len++] = 0x000005e0; -+ ib_cpu[len++] = 0x00000001; - ib_cpu[len++] = 0x00000001; - -- memcpy((ib_cpu + len), uve_slice_header, sizeof(uve_slice_header)); -- len += sizeof(uve_slice_header) / 4; -+ memcpy((ib_cpu + len), uve_nalu_buffer_1, sizeof(uve_nalu_buffer_1)); -+ len += sizeof(uve_nalu_buffer_1) / 4; - -- unsigned luma_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16); -- luma_offset = enc.vbuf.addr; -- chroma_offset = luma_offset + luma_size; -- ib_cpu[len++] = 0x00000088; -- ib_cpu[len++] = 0x0000000d; -- ib_cpu[len++] = 0x00018000; -- ib_cpu[len++] = luma_offset >> 32; -- ib_cpu[len++] = luma_offset; -- ib_cpu[len++] = chroma_offset >> 32; -- ib_cpu[len++] = chroma_offset; -- memcpy((ib_cpu + len), uve_encode_param, sizeof(uve_encode_param)); -- len += sizeof(uve_encode_param) / 4; -+ memcpy((ib_cpu + len), uve_nalu_buffer_2, sizeof(uve_nalu_buffer_2)); -+ len += sizeof(uve_nalu_buffer_2) / 4; - -- memcpy((ib_cpu + len), uve_quality_param, sizeof(uve_quality_param)); -- len += sizeof(uve_quality_param) / 4; -+ memcpy((ib_cpu + len), uve_nalu_buffer_3, sizeof(uve_nalu_buffer_3)); -+ len += sizeof(uve_nalu_buffer_3) / 4; - -- memcpy((ib_cpu + len), uve_intra_refresh, sizeof(uve_intra_refresh)); -- len += sizeof(uve_intra_refresh) / 4; -+ memcpy((ib_cpu + len), uve_nalu_buffer_4, sizeof(uve_nalu_buffer_4)); -+ len += sizeof(uve_nalu_buffer_4) / 4; - -- memcpy((ib_cpu + len), uve_reconstructed_pic_output, sizeof(uve_reconstructed_pic_output)); -- len += sizeof(uve_reconstructed_pic_output) / 4; -+ memcpy((ib_cpu + len), uve_slice_header, sizeof(uve_slice_header)); -+ len += sizeof(uve_slice_header) / 4; - -- memcpy((ib_cpu + len), uve_ctx_buffer, sizeof(uve_ctx_buffer)); -- len += sizeof(uve_ctx_buffer) / 4; -+ ib_cpu[len++] = 0x00000254; -+ ib_cpu[len++] = 0x00000010; - ib_cpu[len++] = enc.cpb.addr >> 32; - ib_cpu[len++] = enc.cpb.addr; -+ memcpy((ib_cpu + len), uve_ctx_buffer, sizeof(uve_ctx_buffer)); -+ len += sizeof(uve_ctx_buffer) / 4; - - memcpy((ib_cpu + len), uve_bitstream_buffer, sizeof(uve_bitstream_buffer)); - len += sizeof(uve_bitstream_buffer) / 4; -+ ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = enc.bs.addr >> 32; - ib_cpu[len++] = enc.bs.addr; -- ib_cpu[len++] = 0x00030000; -+ ib_cpu[len++] = 0x003f4800; -+ ib_cpu[len++] = 0x00000000; - - memcpy((ib_cpu + len), uve_feedback_buffer, sizeof(uve_feedback_buffer)); - len += sizeof(uve_feedback_buffer) / 4; - ib_cpu[len++] = enc.fb.addr >> 32; - ib_cpu[len++] = enc.fb.addr; -- ib_cpu[len++] = 0x00000003; -+ ib_cpu[len++] = 0x00000010; -+ ib_cpu[len++] = 0x00000028; -+ -+ memcpy((ib_cpu + len), uve_feedback_buffer_additional, sizeof(uve_feedback_buffer_additional)); -+ len += sizeof(uve_feedback_buffer_additional) / 4; -+ -+ memcpy((ib_cpu + len), uve_intra_refresh, sizeof(uve_intra_refresh)); -+ len += sizeof(uve_intra_refresh) / 4; -+ -+ memcpy((ib_cpu + len), uve_layer_select, sizeof(uve_layer_select)); -+ len += sizeof(uve_layer_select) / 4; -+ -+ memcpy((ib_cpu + len), uve_rc_layer_init, sizeof(uve_rc_layer_init)); -+ len += sizeof(uve_rc_layer_init) / 4; -+ -+ memcpy((ib_cpu + len), uve_layer_select, sizeof(uve_layer_select)); -+ len += sizeof(uve_layer_select) / 4; - - memcpy((ib_cpu + len), uve_rc_per_pic, sizeof(uve_rc_per_pic)); - len += sizeof(uve_rc_per_pic) / 4; - -+ unsigned luma_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16); -+ luma_offset = enc.vbuf.addr; -+ chroma_offset = luma_offset + luma_size; -+ ib_cpu[len++] = 0x00000054; -+ ib_cpu[len++] = 0x0000000c; -+ ib_cpu[len++] = 0x00000002; -+ ib_cpu[len++] = 0x003f4800; -+ ib_cpu[len++] = luma_offset >> 32; -+ ib_cpu[len++] = luma_offset; -+ ib_cpu[len++] = chroma_offset >> 32; -+ ib_cpu[len++] = chroma_offset; -+ memcpy((ib_cpu + len), uve_encode_param, sizeof(uve_encode_param)); -+ len += sizeof(uve_encode_param) / 4; -+ -+ memcpy((ib_cpu + len), uve_op_speed_enc_mode, sizeof(uve_op_speed_enc_mode)); -+ len += sizeof(uve_op_speed_enc_mode) / 4; -+ - memcpy((ib_cpu + len), uve_op_encode, sizeof(uve_op_encode)); - len += sizeof(uve_op_encode) / 4; - -@@ -491,7 +487,7 @@ static void amdgpu_cs_uvd_enc_destroy(void) - memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); - len += sizeof(uve_task_info) / 4; - ib_cpu[len++] = 0xffffffff; -- ib_cpu[len++] = 0x00000004; -+ ib_cpu[len++] = 0x00000002; - ib_cpu[len++] = 0x00000000; - - memcpy((ib_cpu + len), uve_op_close, sizeof(uve_op_close)); -diff --git a/tests/amdgpu/uve_ib.h b/tests/amdgpu/uve_ib.h -index c24b9e8..9abd406 100644 ---- a/tests/amdgpu/uve_ib.h -+++ b/tests/amdgpu/uve_ib.h -@@ -27,8 +27,8 @@ - static const uint32_t uve_session_info[] = { - 0x00000018, - 0x00000001, -- 0x00000001, - 0x00000000, -+ 0x00010000, - }; - - static const uint32_t uve_task_info[] = { -@@ -37,29 +37,11 @@ static const uint32_t uve_task_info[] = { - }; - - static const uint32_t uve_session_init[] = { -- 0x00000068, -+ 0x00000020, - 0x00000003, -- 0x00000000, -- 0x000000c0, -- 0x00000080, -- 0x00000000, -- 0x00000000, -- 0x00000001, -- 0x00000002, - 0x000000c0, - 0x00000080, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -+ 0x00000020, - 0x00000000, - 0x00000000, - 0x00000000, -@@ -82,8 +64,8 @@ static const uint32_t uve_slice_ctrl[] = { - 0x00000014, - 0x00000006, - 0x00000000, -- 0x00000008, -- 0x00000008, -+ 0x00000006, -+ 0x00000006, - }; - - static const uint32_t uve_spec_misc[] = { -@@ -93,9 +75,9 @@ static const uint32_t uve_spec_misc[] = { - 0x00000000, - 0x00000000, - 0x00000000, -- 0x00000004, - 0x00000000, -- 0x00000005, -+ 0x00000001, -+ 0x00000001, - }; - - static const uint32_t uve_rc_session_init[] = { -@@ -108,54 +90,103 @@ static const uint32_t uve_rc_session_init[] = { - static const uint32_t uve_rc_layer_init[] = { - 0x00000028, - 0x00000009, -+ 0x001e8480, -+ 0x001e8480, -+ 0x0000001e, -+ 0x00000001, -+ 0x0001046a, -+ 0x0001046a, -+ 0x0001046a, -+ 0xaaaaaaaa, -+}; -+ -+static const uint32_t uve_deblocking_filter[] = { -+ 0x00000020, -+ 0x0000000e, -+ 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -+}; -+ -+static const uint32_t uve_quality_params[] = { -+ 0x00000014, -+ 0x0000000d, - 0x00000000, - 0x00000000, - 0x00000000, - }; - --static const uint32_t uve_hw_spec[] = { -- 0x0000007c, -- 0x0000000b, -- 0x00000002, -+static const uint32_t uve_feedback_buffer[] = { -+ 0x0000001c, -+ 0x00000012, - 0x00000000, -+}; -+ -+static const uint32_t uve_feedback_buffer_additional[] = { -+ 0x00000108, -+ 0x00000014, - 0x00000001, -- 0x00000001, -- 0x00000001, -- 0x00000001, -- 0x00000001, -- 0x00000010, -- 0x00000010, -- 0x00000010, -- 0x00000010, -- 0x00000008, -- 0x00000008, -- 0x00000010, - 0x00000010, - 0x00000000, -- 0x00000002, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -- 0x00000001, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -- 0x00000001, -- 0x00000001, --}; -- --static const uint32_t uve_deblocking_filter[] = { -- 0x00000020, -- 0x0000000f, -- 0x00000001, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -@@ -163,19 +194,62 @@ static const uint32_t uve_deblocking_filter[] = { - 0x00000000, - }; - --static const uint32_t uve_feedback_buffer[] = { -- 0x00000014, -- 0x00000014, -+static const uint32_t uve_nalu_buffer_1[] = { -+ 0x00000018, -+ 0x00000013, -+ 0x00000001, -+ 0x00000007, -+ 0x00000001, -+ 0x46011000, -+}; -+ -+static const uint32_t uve_nalu_buffer_2[] = { -+ 0x0000002c, -+ 0x00000013, -+ 0x00000002, -+ 0x0000001b, -+ 0x00000001, -+ 0x40010c01, -+ 0xffff0160, -+ 0x00000300, -+ 0xb0000003, -+ 0x00000300, -+ 0x962c0900, -+}; -+ -+static const uint32_t uve_nalu_buffer_3[] = { -+ 0x00000034, -+ 0x00000013, -+ 0x00000003, -+ 0x00000023, -+ 0x00000001, -+ 0x42010101, -+ 0x60000003, -+ 0x00b00000, -+ 0x03000003, -+ 0x0096a018, -+ 0x2020708f, -+ 0xcb924295, -+ 0x12e08000, -+}; -+ -+static const uint32_t uve_nalu_buffer_4[] = { -+ 0x0000001c, -+ 0x00000013, -+ 0x00000004, -+ 0x0000000b, -+ 0x00000001, -+ 0x4401e0f1, -+ 0x80992000, - }; - --/* TODO - Slice Header*/ - static const uint32_t uve_slice_header[] = { - 0x000000c8, -- 0x0000000c, -- 0x26010000, -+ 0x0000000b, -+ 0x28010000, - 0x40000000, - 0x60000000, -- 0x80000000, -+ 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -@@ -203,7 +277,7 @@ static const uint32_t uve_slice_header[] = { - 0x00000005, - 0x00000000, - 0x00000002, -- 0x00000001, -+ 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -@@ -223,15 +297,146 @@ static const uint32_t uve_slice_header[] = { - }; - - static const uint32_t uve_encode_param[] = { -- 0x00000000, -- 0x00000000, - 0x000000a0, - 0x00000080, - 0x00000000, - 0x00000000, -- 0x00000002, -- 0xffffffff, - 0xffffffff, -+ 0x00000001, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_intra_refresh[] = { -+ 0x00000014, -+ 0x0000000f, -+ 0x00000000, -+ 0x00000000, -+ 0x00000001, -+}; -+ -+static const uint32_t uve_ctx_buffer[] = { -+ 0x00000000, -+ 0x00000000, -+ 0x000000a0, -+ 0x000000a0, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -@@ -250,55 +455,34 @@ static const uint32_t uve_encode_param[] = { - 0x00000000, - 0x00000000, - 0x00000000, --}; -- --static const uint32_t uve_quality_param[] = { -- 0x00000014, -- 0x0000000e, - 0x00000000, - 0x00000000, - 0x00000000, --}; -- --static const uint32_t uve_intra_refresh[] = { -- 0x00000014, -- 0x00000010, - 0x00000000, - 0x00000000, -- 0x00000004, --}; -- --static const uint32_t uve_reconstructed_pic_output[] = { -- 0x00000020, -- 0x00000011, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, --}; -- --static const uint32_t uve_ctx_buffer[] = { -- 0x00000010, -- 0x00000012, - }; - - static const uint32_t uve_bitstream_buffer[] = { -- 0x00000014, -- 0x00000013, -+ 0x0000001c, -+ 0x00000011, - }; - - static const uint32_t uve_rc_per_pic[] = { - 0x00000024, - 0x0000000a, - 0x0000001a, -- 0x00000014, -- 0x0000002D, - 0x00000000, -+ 0x00000033, - 0x00000000, - 0x00000000, - 0x00000000, -+ 0x00000001, - }; - - static const uint32_t uve_op_init[] = { -@@ -320,4 +504,24 @@ static const uint32_t uve_op_init_rc[] = { - 0x00000008, - 0x08000004, - }; -+ -+static const uint32_t uve_op_init_rc_vbv_level[] = { -+ 0x00000008, -+ 0x08000005, -+}; -+ -+static const uint32_t uve_op_speed_enc_mode[] = { -+ 0x00000008, -+ 0x08000006, -+}; -+ -+static const uint32_t uve_op_balance_enc_mode[] = { -+ 0x00000008, -+ 0x08000007, -+}; -+ -+static const uint32_t uve_op_quality_enc_mode[] = { -+ 0x00000008, -+ 0x08000008, -+}; - #endif /*_uve_ib_h*/ --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm_2.4.%.bbappend b/meta-v1000/recipes-graphics/drm/libdrm_2.4.%.bbappend new file mode 100644 index 00000000..b17f5c62 --- /dev/null +++ b/meta-v1000/recipes-graphics/drm/libdrm_2.4.%.bbappend @@ -0,0 +1,52 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/${BPN}:" + +SRC_URI_append = " file://0001-amdgpu-Implement-SVM-v3.patch \ + file://0002-amdgpu-SVM-test-v3.patch \ + file://0003-amdgpu-Implement-multiGPU-SVM-support-v3.patch \ + file://0004-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v4.patch \ + file://0005-amdgpu-add-query-for-aperture-va-range.patch \ + file://0006-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag-v2.patch \ + file://0007-amdgpu-add-sparse-flag-for-bo-creatation-v2.patch \ + file://0008-amdgpu-add-amdgpu_query_capability-interface-v2.patch \ + file://0009-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch \ + file://0010-amdgpu-support-alloc-va-from-range-v2.patch \ + file://0011-tests-amdgpu-add-alloc-va-from-range-test-v2.patch \ + file://0012-amdgpu-change-max-allocation.patch \ + file://0013-amdgpu-add-bo-handle-to-hash-table-when-cpu-mapping.patch \ + file://0014-amdgpu-add-amdgpu_bo_inc_ref-function.patch \ + file://0015-amdgpu-Make-amdgpu_get_auth-to-non-static.patch \ + file://0016-amdgpu-Add-interface-amdgpu_get_fb_id-v2.patch \ + file://0017-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id-v2.patch \ + file://0018-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch \ + file://0019-drm-amdgpu-add-freesync-ioctl-defines.patch \ + file://0020-amdgpu-implement-direct-gma.patch \ + file://0021-tests-amdgpu-add-direct-gma-test.patch \ + file://0022-amdgpu-add-new-semaphore-support-v2.patch \ + file://0023-implement-import-export-sem.patch \ + file://0024-test-case-for-export-import-sem.patch \ + file://0025-amdgpu-Sparse-resource-support-for-Vulkan-v2.patch \ + file://0029-amdgpu-support-16-ibs-per-submit-for-PAL-SRIOV.patch \ + file://0030-amdgpu-hybrid-add-a-flag-of-memory-allcation-from-to.patch \ + file://0031-amdgpu-unify-dk-drm-header-changes.patch \ + file://0032-amdgpu-add-interface-for-reserve-unserve-vmid-v2.patch \ + file://0033-amdgpu-HYBRID-add-AMDGPU_CAPABILITY_SSG_FLAG.patch \ + file://0037-tests-amdgpu-HYBRID-add-SSG-unit-test.patch \ + file://0044-amdgpu-HYBRID-change-to-use-amdgpu_bo_free.patch \ + file://amdgpu.ids \ +" + +EXTRA_OECONF = "--disable-cairo-tests \ + --enable-omap-experimental-api \ + --enable-install-test-programs \ + --disable-manpages \ + --disable-valgrind \ + --enable-amdgpu \ + --enable-radeon \ + " + +do_install_append() { + cp ${S}/include/drm/amdgpu_drm.h ${D}/usr/include/libdrm + install -vd ${D}/usr/share/libdrm + cp ${WORKDIR}/amdgpu.ids ${D}/usr/share/libdrm +} + diff --git a/meta-v1000/recipes-graphics/drm/libdrm_git.bb b/meta-v1000/recipes-graphics/drm/libdrm_git.bb deleted file mode 100644 index a69f15c2..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm_git.bb +++ /dev/null @@ -1,101 +0,0 @@ -SUMMARY = "Userspace interface to the kernel DRM services" -DESCRIPTION = "The runtime library for accessing the kernel DRM services. DRM \ -stands for \"Direct Rendering Manager\", which is the kernel portion of the \ -\"Direct Rendering Infrastructure\" (DRI). DRI is required for many hardware \ -accelerated OpenGL drivers." - -HOMEPAGE = "http://dri.freedesktop.org" -SECTION = "x11/base" -LICENSE = "MIT" -LIC_FILES_CHKSUM_amd = "file://xf86drm.c;beginline=9;endline=32;md5=c8a3b961af7667c530816761e949dc71" -PROVIDES = "drm" -PV = "git" - -inherit autotools pkgconfig - -SRCREV = "23e234a3503f51b9d9c585123d33b936f522808d" -DEPENDS = "libpthread-stubs udev libpciaccess freetype libxext cairo fontconfig libxrender libpng pixman" - -SRC_URI = "git://anongit.freedesktop.org/mesa/drm;branch=master \ - file://0001-amdgpu-Implement-SVM-v3.patch \ - file://0002-amdgpu-SVM-test-v3.patch \ - file://0003-amdgpu-Implement-multiGPU-SVM-support-v3.patch \ - file://0004-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v4.patch \ - file://0005-amdgpu-add-query-for-aperture-va-range.patch \ - file://0006-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag-v2.patch \ - file://0007-amdgpu-add-sparse-flag-for-bo-creatation-v2.patch \ - file://0008-amdgpu-add-amdgpu_query_capability-interface-v2.patch \ - file://0009-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch \ - file://0010-amdgpu-support-alloc-va-from-range-v2.patch \ - file://0011-tests-amdgpu-add-alloc-va-from-range-test-v2.patch \ - file://0012-amdgpu-change-max-allocation.patch \ - file://0013-amdgpu-add-bo-handle-to-hash-table-when-cpu-mapping.patch \ - file://0014-amdgpu-add-amdgpu_bo_inc_ref-function.patch \ - file://0015-amdgpu-Make-amdgpu_get_auth-to-non-static.patch \ - file://0016-amdgpu-Add-interface-amdgpu_get_fb_id-v2.patch \ - file://0017-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id-v2.patch \ - file://0018-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch \ - file://0019-drm-amdgpu-add-freesync-ioctl-defines.patch \ - file://0020-amdgpu-implement-direct-gma.patch \ - file://0021-tests-amdgpu-add-direct-gma-test.patch \ - file://0022-amdgpu-add-new-semaphore-support-v2.patch \ - file://0023-implement-import-export-sem.patch \ - file://0024-test-case-for-export-import-sem.patch \ - file://0025-amdgpu-Sparse-resource-support-for-Vulkan-v2.patch \ - file://0026-tests-amdgpu-add-uvd-enc-unit-tests-v2.patch \ - file://0027-tests-amdgpu-add-uve-ib-header.patch \ - file://0028-tests-amdgpu-implement-hevc-encode-test-v2.patch \ - file://0029-amdgpu-support-16-ibs-per-submit-for-PAL-SRIOV.patch \ - file://0030-amdgpu-hybrid-add-a-flag-of-memory-allcation-from-to.patch \ - file://0031-amdgpu-unify-dk-drm-header-changes.patch \ - file://0032-amdgpu-add-interface-for-reserve-unserve-vmid-v2.patch \ - file://0033-amdgpu-HYBRID-add-AMDGPU_CAPABILITY_SSG_FLAG.patch \ - file://0034-tests-amdgpu-bypass-UVD-CS-tests-on-raven.patch \ - file://0035-tests-amdgpu-bypass-UVD-ENC-tests-on-raven.patch \ - file://0036-tests-amdgpu-bypass-VCE-tests-on-raven.patch \ - file://0037-tests-amdgpu-HYBRID-add-SSG-unit-test.patch \ - file://0038-amdgpu-Add-gpu-always-on-cu-bitmap.patch \ - file://0039-test-amdgpu-fix-test-failure-for-SI.patch \ - file://0040-drm-fix-missing-mutex-unlock-before-return.patch \ - file://0041-drm-fix-race-issue-between-two-bo-functions-v2.patch \ - file://0042-amdgpu-fix-potential-deadlock.patch \ - file://0043-Revert-amdgpu-fix-potential-deadlock.patch \ - file://0044-amdgpu-HYBRID-change-to-use-amdgpu_bo_free.patch \ - file://0045-amdgpu-merge-and-cleanup-amdgpu_bo_free.patch \ - file://0046-tests-amdgpu-update-uvd-enc-test-for-new-fw.patch \ - file://amdgpu.ids \ -" - -S = "${WORKDIR}/git" - -EXTRA_OECONF = "--disable-cairo-tests \ - --enable-omap-experimental-api \ - --enable-install-test-programs \ - --disable-manpages \ - --disable-valgrind \ - --enable-amdgpu \ - --enable-radeon \ - " - -ALLOW_EMPTY_${PN}-drivers = "1" -PACKAGES =+ "${PN}-tests ${PN}-drivers ${PN}-radeon ${PN}-nouveau ${PN}-omap \ - ${PN}-intel ${PN}-exynos ${PN}-kms ${PN}-freedreno ${PN}-amdgpu" - -RRECOMMENDS_${PN}-drivers = "${PN}-radeon ${PN}-nouveau ${PN}-omap ${PN}-intel \ - ${PN}-exynos ${PN}-freedreno ${PN}-amdgpu" - -FILES_${PN}-tests = "${bindir}/dr* ${bindir}/mode* ${bindir}/*test" -FILES_${PN}-radeon = "${libdir}/libdrm_radeon.so.*" -FILES_${PN}-nouveau = "${libdir}/libdrm_nouveau.so.*" -FILES_${PN}-omap = "${libdir}/libdrm_omap.so.*" -FILES_${PN}-intel = "${libdir}/libdrm_intel.so.*" -FILES_${PN}-exynos = "${libdir}/libdrm_exynos.so.*" -FILES_${PN}-kms = "${libdir}/libkms*.so.*" -FILES_${PN}-freedreno = "${libdir}/libdrm_freedreno.so.*" -FILES_${PN}-amdgpu = "${libdir}/libdrm_amdgpu.so.*" - -do_install_append() { - cp ${S}/include/drm/amdgpu_drm.h ${D}/usr/include/libdrm - install -vd ${D}/usr/share/libdrm - cp ${WORKDIR}/amdgpu.ids ${D}/usr/share/libdrm -} diff --git a/meta-v1000/recipes-graphics/lunarg-sdk/vulkan-samples_1.0.65.bb b/meta-v1000/recipes-graphics/lunarg-sdk/vulkan-samples_1.0.65.bb index 5611cd63..3a58fbf8 100644 --- a/meta-v1000/recipes-graphics/lunarg-sdk/vulkan-samples_1.0.65.bb +++ b/meta-v1000/recipes-graphics/lunarg-sdk/vulkan-samples_1.0.65.bb @@ -3,7 +3,7 @@ DESCRIPTION = "This project is a collection \ of Vulkan C++ sample applications." SECTION = "graphics" HOMEPAGE = "https://github.com/LunarG/VulkanSamples" -DEPENDS = "vulkan-loader-layers glslang" +DEPENDS = "vulkan-loader-layers glslang glslang-native libxkbcommon" inherit cmake python3native diff --git a/meta-v1000/recipes-graphics/lunarg-sdk/vulkan-tools_1.0.65.bb b/meta-v1000/recipes-graphics/lunarg-sdk/vulkan-tools_1.0.65.bb index d26d7862..0e41c56d 100644 --- a/meta-v1000/recipes-graphics/lunarg-sdk/vulkan-tools_1.0.65.bb +++ b/meta-v1000/recipes-graphics/lunarg-sdk/vulkan-tools_1.0.65.bb @@ -48,8 +48,8 @@ INSANE_SKIP_${PN}-layer-libs = "ldflags" # Conditional building of vktraceviewer QTBITS ?= "${@bb.utils.contains('BBFILE_COLLECTIONS', 'qt5-layer', 'cmake_qt5', '',d)}" inherit ${QTBITS} -DEPENDS += "${@base_conditional('QTBITS', '', '', 'libxcb qtsvg', d)}" -RDEPENDS_${PN}_append = " ${@base_conditional('QTBITS', '', '', 'qtsvg', d)}" +DEPENDS += "${@oe.utils.conditional('QTBITS', '', '', 'libxcb qtsvg', d)}" +RDEPENDS_${PN}_append = " ${@oe.utils.conditional('QTBITS', '', '', 'qtsvg', d)}" do_install_append() { if [ "${QTBITS}" != "" ] then diff --git a/meta-v1000/recipes-graphics/mesa/mesa/0001-st-omx-enc-Correct-the-timestamping.patch b/meta-v1000/recipes-graphics/mesa/mesa/0001-st-omx-enc-Correct-the-timestamping.patch index 6542098c..41e06404 100644 --- a/meta-v1000/recipes-graphics/mesa/mesa/0001-st-omx-enc-Correct-the-timestamping.patch +++ b/meta-v1000/recipes-graphics/mesa/mesa/0001-st-omx-enc-Correct-the-timestamping.patch @@ -8,13 +8,13 @@ while pushing bitstrema buffer to the omx client. Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com> --- - src/gallium/state_trackers/omx/vid_enc.c | 3 +++ + src/gallium/state_trackers/omx_bellagio/vid_enc.c | 3 +++ 1 file changed, 3 insertions(+) -diff --git a/src/gallium/state_trackers/omx/vid_enc.c b/src/gallium/state_trackers/omx/vid_enc.c +diff --git a/src/gallium/state_trackers/omx_bellagio/vid_enc.c b/src/gallium/state_trackers/omx_bellagio/vid_enc.c index 1a4fb62..9004ddd 100644 ---- a/src/gallium/state_trackers/omx/vid_enc.c -+++ b/src/gallium/state_trackers/omx/vid_enc.c +--- a/src/gallium/state_trackers/omx_bellagio/vid_enc.c ++++ b/src/gallium/state_trackers/omx_bellagio/vid_enc.c @@ -58,6 +58,7 @@ struct encode_task { struct list_head list; diff --git a/meta-v1000/recipes-graphics/mesa/mesa/0002-st-omx-enc-Modularize-the-Encoding-task.patch b/meta-v1000/recipes-graphics/mesa/mesa/0002-st-omx-enc-Modularize-the-Encoding-task.patch index c692b70a..1e58435c 100644 --- a/meta-v1000/recipes-graphics/mesa/mesa/0002-st-omx-enc-Modularize-the-Encoding-task.patch +++ b/meta-v1000/recipes-graphics/mesa/mesa/0002-st-omx-enc-Modularize-the-Encoding-task.patch @@ -7,13 +7,13 @@ Prepare for integrating the FRC logic in encoder Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com> --- - src/gallium/state_trackers/omx/vid_enc.c | 78 ++++++++++++++++++-------------- + src/gallium/state_trackers/omx_bellagio/vid_enc.c | 78 ++++++++++++++++++-------------- 1 file changed, 44 insertions(+), 34 deletions(-) -diff --git a/src/gallium/state_trackers/omx/vid_enc.c b/src/gallium/state_trackers/omx/vid_enc.c +diff --git a/src/gallium/state_trackers/omx_bellagio/vid_enc.c b/src/gallium/state_trackers/omx_bellagio/vid_enc.c index 9004ddd..a6502ce 100644 ---- a/src/gallium/state_trackers/omx/vid_enc.c -+++ b/src/gallium/state_trackers/omx/vid_enc.c +--- a/src/gallium/state_trackers/omx_bellagio/vid_enc.c ++++ b/src/gallium/state_trackers/omx_bellagio/vid_enc.c @@ -1138,44 +1138,13 @@ static void enc_ClearBframes(omx_base_PortType *port, struct input_buf_private * enc_MoveTasks(&priv->b_frames, &inp->tasks); } diff --git a/meta-v1000/recipes-graphics/mesa/mesa/0003-st-omx-enc-Support-framerate-conversion.patch b/meta-v1000/recipes-graphics/mesa/mesa/0003-st-omx-enc-Support-framerate-conversion.patch index 89f1348a..0cf39d96 100644 --- a/meta-v1000/recipes-graphics/mesa/mesa/0003-st-omx-enc-Support-framerate-conversion.patch +++ b/meta-v1000/recipes-graphics/mesa/mesa/0003-st-omx-enc-Support-framerate-conversion.patch @@ -18,14 +18,14 @@ timestamps. Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com> --- - src/gallium/state_trackers/omx/vid_enc.c | 194 +++++++++++++++++++++++++++++-- - src/gallium/state_trackers/omx/vid_enc.h | 7 ++ + src/gallium/state_trackers/omx_bellagio/vid_enc.c | 194 +++++++++++++++++++++++++++++-- + src/gallium/state_trackers/omx_bellagio/vid_enc.h | 7 ++ 2 files changed, 192 insertions(+), 9 deletions(-) -diff --git a/src/gallium/state_trackers/omx/vid_enc.c b/src/gallium/state_trackers/omx/vid_enc.c +diff --git a/src/gallium/state_trackers/omx_bellagio/vid_enc.c b/src/gallium/state_trackers/omx_bellagio/vid_enc.c index a6502ce..ec3b281 100644 ---- a/src/gallium/state_trackers/omx/vid_enc.c -+++ b/src/gallium/state_trackers/omx/vid_enc.c +--- a/src/gallium/state_trackers/omx_bellagio/vid_enc.c ++++ b/src/gallium/state_trackers/omx_bellagio/vid_enc.c @@ -54,11 +54,19 @@ #include "entrypoint.h" #include "vid_enc.h" @@ -311,10 +311,10 @@ index a6502ce..ec3b281 100644 - output->nFlags = OMX_BUFFERFLAG_ENDOFFRAME; + output->nFlags = OMX_BUFFERFLAG_ENDOFFRAME; } -diff --git a/src/gallium/state_trackers/omx/vid_enc.h b/src/gallium/state_trackers/omx/vid_enc.h +diff --git a/src/gallium/state_trackers/omx_bellagio/vid_enc.h b/src/gallium/state_trackers/omx_bellagio/vid_enc.h index a833744..4b73f68 100644 ---- a/src/gallium/state_trackers/omx/vid_enc.h -+++ b/src/gallium/state_trackers/omx/vid_enc.h +--- a/src/gallium/state_trackers/omx_bellagio/vid_enc.h ++++ b/src/gallium/state_trackers/omx_bellagio/vid_enc.h @@ -74,6 +74,13 @@ DERIVEDCLASS(vid_enc_PrivateType, omx_base_filter_PrivateType) struct list_head used_tasks; \ struct list_head b_frames; \ diff --git a/meta-v1000/recipes-graphics/mesa/mesa/0004-st-mesa-Reverting-patches-that-solved-perf-issues-wi.patch b/meta-v1000/recipes-graphics/mesa/mesa/0004-st-mesa-Reverting-patches-that-solved-perf-issues-wi.patch index e06e2750..d9904b63 100644 --- a/meta-v1000/recipes-graphics/mesa/mesa/0004-st-mesa-Reverting-patches-that-solved-perf-issues-wi.patch +++ b/meta-v1000/recipes-graphics/mesa/mesa/0004-st-mesa-Reverting-patches-that-solved-perf-issues-wi.patch @@ -1,7 +1,7 @@ -From e286b9139834d21c6d3e13e62535f7a7d627cbcb Mon Sep 17 00:00:00 2001 -From: Indrajit Das <indrajit-kumar.das@amd.com> -Date: Tue, 1 Aug 2017 10:49:01 +0530 -Subject: [PATCH] st/mesa: Reverting patches that solved perf issues with mesa +From 345436540fbba97a22170c7fff4bed1d461d7fd7 Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Fri, 15 Dec 2017 15:35:08 +0500 +Subject: [PATCH] st/mesa: Reverting patches that solved perf issues with mesa 12.0.3 This patch reverts below patches to solve performance issue @@ -19,6 +19,7 @@ patch4: Subject: st/mesa: fix reference counting bug in st_vdpau Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Awais Belal <awais_belal@mentor.com> --- src/gallium/state_trackers/vdpau/output.c | 2 +- src/mesa/state_tracker/st_texture.h | 6 + @@ -39,10 +40,10 @@ index 8ef8268..c13bbaf 100644 mtx_lock(&dev->mutex); diff --git a/src/mesa/state_tracker/st_texture.h b/src/mesa/state_tracker/st_texture.h -index 8448f4c..8bcca89 100644 +index 8b549b8..6ed4294 100644 --- a/src/mesa/state_tracker/st_texture.h +++ b/src/mesa/state_tracker/st_texture.h -@@ -84,6 +84,12 @@ struct st_texture_object +@@ -97,6 +97,12 @@ struct st_texture_object */ GLuint lastLevel; @@ -56,7 +57,7 @@ index 8448f4c..8bcca89 100644 unsigned int validated_last_level; diff --git a/src/mesa/state_tracker/st_vdpau.c b/src/mesa/state_tracker/st_vdpau.c -index 0273815..827e1f0 100644 +index 19611e7..aeb66df 100644 --- a/src/mesa/state_tracker/st_vdpau.c +++ b/src/mesa/state_tracker/st_vdpau.c @@ -38,6 +38,7 @@ @@ -276,7 +277,7 @@ index 0273815..827e1f0 100644 return; } -@@ -235,18 +133,20 @@ st_vdpau_map_surface(struct gl_context *ctx, GLenum target, GLenum access, +@@ -235,19 +133,21 @@ st_vdpau_map_surface(struct gl_context *ctx, GLenum target, GLenum access, st_texture_release_all_sampler_views(st, stObj); pipe_resource_reference(&stImage->pt, res); @@ -284,6 +285,7 @@ index 0273815..827e1f0 100644 + stObj->height0 = res->height0; + stObj->depth0 = 1; stObj->surface_format = res->format; + stObj->level_override = 0; stObj->layer_override = layer_override; _mesa_dirty_texobj(ctx, texObj); @@ -300,5 +302,5 @@ index 0273815..827e1f0 100644 struct st_context *st = st_context(ctx); struct st_texture_object *stObj = st_texture_object(texObj); -- -2.7.4 +2.11.1 diff --git a/meta-v1000/recipes-graphics/mesa/mesa/0006-st-omx-handle-invalid-timestamps-better-for-frc.patch b/meta-v1000/recipes-graphics/mesa/mesa/0006-st-omx-handle-invalid-timestamps-better-for-frc.patch index 21c0fa25..38da60c5 100644 --- a/meta-v1000/recipes-graphics/mesa/mesa/0006-st-omx-handle-invalid-timestamps-better-for-frc.patch +++ b/meta-v1000/recipes-graphics/mesa/mesa/0006-st-omx-handle-invalid-timestamps-better-for-frc.patch @@ -7,14 +7,14 @@ Handle buffers with 0 timestamps better by keeping track of the en time of the previous buffer and assuming the 0 timestamp buffer goes right after the previous one. --- - src/gallium/state_trackers/omx/vid_dec.c | 1 + - src/gallium/state_trackers/omx/vid_enc.c | 4 ++++ + src/gallium/state_trackers/omx_bellagio/vid_dec.c | 1 + + src/gallium/state_trackers/omx_bellagio/vid_enc.c | 4 ++++ 2 files changed, 5 insertions(+) -diff --git a/src/gallium/state_trackers/omx/vid_dec.c b/src/gallium/state_trackers/omx/vid_dec.c +diff --git a/src/gallium/state_trackers/omx_bellagio/vid_dec.c b/src/gallium/state_trackers/omx_bellagio/vid_dec.c index 313bc0a..e0d3043 100644 ---- a/src/gallium/state_trackers/omx/vid_dec.c -+++ b/src/gallium/state_trackers/omx/vid_dec.c +--- a/src/gallium/state_trackers/omx_bellagio/vid_dec.c ++++ b/src/gallium/state_trackers/omx_bellagio/vid_dec.c @@ -656,6 +656,7 @@ static void vid_dec_FrameDecoded(OMX_COMPONENTTYPE *comp, OMX_BUFFERHEADERTYPE* } output->nFilledLen = output->nAllocLen; @@ -23,10 +23,10 @@ index 313bc0a..e0d3043 100644 } if (eos && input->pInputPortPrivate) -diff --git a/src/gallium/state_trackers/omx/vid_enc.c b/src/gallium/state_trackers/omx/vid_enc.c +diff --git a/src/gallium/state_trackers/omx_bellagio/vid_enc.c b/src/gallium/state_trackers/omx_bellagio/vid_enc.c index ec3b281..c80dcd5 100644 ---- a/src/gallium/state_trackers/omx/vid_enc.c -+++ b/src/gallium/state_trackers/omx/vid_enc.c +--- a/src/gallium/state_trackers/omx_bellagio/vid_enc.c ++++ b/src/gallium/state_trackers/omx_bellagio/vid_enc.c @@ -1332,6 +1332,10 @@ static OMX_ERRORTYPE vid_enc_EncodeFrame(omx_base_PortType *port, OMX_BUFFERHEAD /* Two frames are available to make a choice */ diff --git a/meta-v1000/recipes-graphics/mesa/mesa/0007-Revert-st-mesa-Reverting-patches-that-solved-perf-is.patch b/meta-v1000/recipes-graphics/mesa/mesa/0007-Revert-st-mesa-Reverting-patches-that-solved-perf-is.patch index 8a5dc15f..96fecf77 100644 --- a/meta-v1000/recipes-graphics/mesa/mesa/0007-Revert-st-mesa-Reverting-patches-that-solved-perf-is.patch +++ b/meta-v1000/recipes-graphics/mesa/mesa/0007-Revert-st-mesa-Reverting-patches-that-solved-perf-is.patch @@ -1,10 +1,13 @@ -From 543a654b9ad9016c0e01a33a6f2b41a0935e1d80 Mon Sep 17 00:00:00 2001 -From: Indrajit Das <indrajit-kumar.das@amd.com> -Date: Thu, 21 Sep 2017 11:49:32 +0530 -Subject: [PATCH 7/7] Revert "st/mesa: Reverting patches that solved perf - issues with mesa 12.0.3" +From f9affcd19f4f4695084399aeaaa2d1e1344e7b94 Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Fri, 15 Dec 2017 15:40:52 +0500 +Subject: [PATCH] Revert "st/mesa: Reverting patches that solved perf issues + with mesa 12.0.3" This reverts commit 6102e577d8f2816771920a014c5d80ca62dafb8d. + +Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com> +Signed-off-by: Awais Belal <awais_belal@mentor.com> --- src/gallium/state_trackers/vdpau/output.c | 2 +- src/mesa/state_tracker/st_texture.h | 6 - @@ -25,10 +28,10 @@ index c13bbaf..8ef8268 100644 mtx_lock(&dev->mutex); diff --git a/src/mesa/state_tracker/st_texture.h b/src/mesa/state_tracker/st_texture.h -index 8bcca89..8448f4c 100644 +index 6ed4294..8b549b8 100644 --- a/src/mesa/state_tracker/st_texture.h +++ b/src/mesa/state_tracker/st_texture.h -@@ -84,12 +84,6 @@ struct st_texture_object +@@ -97,12 +97,6 @@ struct st_texture_object */ GLuint lastLevel; @@ -42,7 +45,7 @@ index 8bcca89..8448f4c 100644 unsigned int validated_last_level; diff --git a/src/mesa/state_tracker/st_vdpau.c b/src/mesa/state_tracker/st_vdpau.c -index 827e1f0..0273815 100644 +index aeb66df..19611e7 100644 --- a/src/mesa/state_tracker/st_vdpau.c +++ b/src/mesa/state_tracker/st_vdpau.c @@ -38,7 +38,6 @@ @@ -262,7 +265,7 @@ index 827e1f0..0273815 100644 return; } -@@ -133,20 +235,18 @@ st_vdpau_map_surface(struct gl_context *ctx, GLenum target, GLenum access, +@@ -133,21 +235,19 @@ st_vdpau_map_surface(struct gl_context *ctx, GLenum target, GLenum access, st_texture_release_all_sampler_views(st, stObj); pipe_resource_reference(&stImage->pt, res); @@ -270,6 +273,7 @@ index 827e1f0..0273815 100644 - stObj->height0 = res->height0; - stObj->depth0 = 1; stObj->surface_format = res->format; + stObj->level_override = 0; stObj->layer_override = layer_override; _mesa_dirty_texobj(ctx, texObj); @@ -286,5 +290,5 @@ index 827e1f0..0273815 100644 struct st_context *st = st_context(ctx); struct st_texture_object *stObj = st_texture_object(texObj); -- -2.7.4 +2.11.1 diff --git a/meta-v1000/recipes-graphics/mesa/mesa_17.3.%.bbappend b/meta-v1000/recipes-graphics/mesa/mesa_17.3.%.bbappend new file mode 100644 index 00000000..e819463b --- /dev/null +++ b/meta-v1000/recipes-graphics/mesa/mesa_17.3.%.bbappend @@ -0,0 +1,11 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" + +MESA_LLVM_RELEASE_v1000 = "6.0" + +SRC_URI_append_v1000 = " file://0001-st-omx-enc-Correct-the-timestamping.patch \ + file://0002-st-omx-enc-Modularize-the-Encoding-task.patch \ + file://0003-st-omx-enc-Support-framerate-conversion.patch \ + file://0004-st-mesa-Reverting-patches-that-solved-perf-issues-wi.patch \ + file://0005-Added-the-workaround-fix-for-the-opengl-CTS-failure..patch \ + file://0006-st-omx-handle-invalid-timestamps-better-for-frc.patch \ + file://0007-Revert-st-mesa-Reverting-patches-that-solved-perf-is.patch"
\ No newline at end of file diff --git a/meta-v1000/recipes-graphics/mesa/mesa_git.bbappend b/meta-v1000/recipes-graphics/mesa/mesa_git.bbappend deleted file mode 100644 index f6ad3fee..00000000 --- a/meta-v1000/recipes-graphics/mesa/mesa_git.bbappend +++ /dev/null @@ -1,23 +0,0 @@ -FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" - -SRCREV_v1000 = "b8dd69e1b49a5c4c5c82e34f804a97f7448ff6c3" -LIC_FILES_CHKSUM_v1000 = "file://docs/license.html;md5=725f991a1cc322aa7a0cd3a2016621c4" -PV_v1000 = "17.3.0+git${SRCPV}" - -MESA_LLVM_RELEASE_v1000 = "6.0" - -PACKAGECONFIG_append_v1000 = " dri3" - -SRC_URI_v1000 = "\ - git://anongit.freedesktop.org/mesa/mesa;branch=master \ - file://0001-st-omx-enc-Correct-the-timestamping.patch \ - file://0002-st-omx-enc-Modularize-the-Encoding-task.patch \ - file://0003-st-omx-enc-Support-framerate-conversion.patch \ - file://0004-st-mesa-Reverting-patches-that-solved-perf-issues-wi.patch \ - file://0005-Added-the-workaround-fix-for-the-opengl-CTS-failure..patch \ - file://0006-st-omx-handle-invalid-timestamps-better-for-frc.patch \ - file://0007-Revert-st-mesa-Reverting-patches-that-solved-perf-is.patch \ -" - -MESA_CRYPTO_v1000 = "" - |