1 files changed, 49 insertions, 0 deletions
diff --git a/meta-snowyowl/recipes-kernel/linux/files/0487-x86-mce-AMD-Use-msr_stat-when-clearing-MCA_STATUS.patch b/meta-snowyowl/recipes-kernel/linux/files/0487-x86-mce-AMD-Use-msr_stat-when-clearing-MCA_STATUS.patch
new file mode 100644
index 00000000..3bc5cb8c
--- /dev/null
+++ b/meta-snowyowl/recipes-kernel/linux/files/0487-x86-mce-AMD-Use-msr_stat-when-clearing-MCA_STATUS.patch
@@ -0,0 +1,49 @@
+From 66004d7800e0310fac27a01e4139cb0c798e3c8d Mon Sep 17 00:00:00 2001
+From: Yazen Ghannam <yazen.ghannam@amd.com>
+Date: Tue, 13 Jun 2017 18:28:28 +0200
+Subject: [PATCH 07/10] x86/mce/AMD: Use msr_stat when clearing MCA_STATUS
+
+The value of MCA_STATUS is used as the MSR when clearing MCA_STATUS.
+
+This may cause the following warning:
+
+ unchecked MSR access error: WRMSR to 0x11b (tried to write 0x0000000000000000)
+ Call Trace:
+  <IRQ>
+  smp_threshold_interrupt()
+  threshold_interrupt()
+
+Use msr_stat instead which has the MSR address.
+
+Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: Borislav Petkov <bp@alien8.de>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Tony Luck <tony.luck@intel.com>
+Cc: linux-edac <linux-edac@vger.kernel.org>
+Fixes: 37d43acfd79f ("x86/mce/AMD: Redo error logging from APIC LVT interrupt handlers")
+Link: http://lkml.kernel.org/r/20170613162835.30750-2-bp@alien8.de
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com>
+---
+ arch/x86/kernel/cpu/mcheck/mce_amd.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
+index 82d0c1c..a4e38c4 100644
+--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
++++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
+@@ -816,7 +816,7 @@ _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
+ 
+ 	__log_error(bank, status, addr, misc);
+ 
+-	wrmsrl(status, 0);
++	wrmsrl(msr_stat, 0);
+ 
+ 	return status & MCI_STATUS_DEFERRED;
+ }
+-- 
+2.7.4
+