aboutsummaryrefslogtreecommitdiffstats
path: root/meta-amdfalconx86/recipes-kernel/linux/linux-yocto/0743-drm-amd-powerplay-enable-clock-gating-for-Fiji.patch
diff options
context:
space:
mode:
Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/linux-yocto/0743-drm-amd-powerplay-enable-clock-gating-for-Fiji.patch')
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/linux-yocto/0743-drm-amd-powerplay-enable-clock-gating-for-Fiji.patch35
1 files changed, 35 insertions, 0 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/linux-yocto/0743-drm-amd-powerplay-enable-clock-gating-for-Fiji.patch b/meta-amdfalconx86/recipes-kernel/linux/linux-yocto/0743-drm-amd-powerplay-enable-clock-gating-for-Fiji.patch
new file mode 100644
index 00000000..31ffd44f
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/linux-yocto/0743-drm-amd-powerplay-enable-clock-gating-for-Fiji.patch
@@ -0,0 +1,35 @@
+From dc1656068b40814aa85206098ad358609a281fc4 Mon Sep 17 00:00:00 2001
+From: Eric Huang <JinHuiEric.Huang@amd.com>
+Date: Thu, 12 Nov 2015 17:30:52 -0500
+Subject: [PATCH 0743/1050] drm/amd/powerplay: enable clock gating for Fiji.
+
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
+Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+index c96b458..45997e6 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+@@ -917,7 +917,14 @@ static int fiji_start_smu(struct pp_smumgr *smumgr)
+ }
+
+ /* To initialize all clock gating before RLC loaded and running.*/
+- /*PECI_InitClockGating(peci);*/
++ cgs_set_clockgating_state(smumgr->device,
++ AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
++ cgs_set_clockgating_state(smumgr->device,
++ AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
++ cgs_set_clockgating_state(smumgr->device,
++ AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
++ cgs_set_clockgating_state(smumgr->device,
++ AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
+
+ /* Setup SoftRegsStart here for register lookup in case
+ * DummyBackEnd is used and ProcessFirmwareHeader is not executed
+--
+1.9.1
+