diff options
Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/linux-yocto/0609-drm-amdgpu-clean-up-pageflip-interrupt-handling.patch')
| -rw-r--r-- | meta-amdfalconx86/recipes-kernel/linux/linux-yocto/0609-drm-amdgpu-clean-up-pageflip-interrupt-handling.patch | 325 |
1 files changed, 325 insertions, 0 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/linux-yocto/0609-drm-amdgpu-clean-up-pageflip-interrupt-handling.patch b/meta-amdfalconx86/recipes-kernel/linux/linux-yocto/0609-drm-amdgpu-clean-up-pageflip-interrupt-handling.patch new file mode 100644 index 00000000..a3849c6c --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/linux-yocto/0609-drm-amdgpu-clean-up-pageflip-interrupt-handling.patch @@ -0,0 +1,325 @@ +From e9bb44d265a9957190d32f0b2f011eb590c03cef Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 9 Oct 2015 11:38:49 -0400 +Subject: [PATCH 0609/1050] drm/amdgpu: clean up pageflip interrupt handling +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Check to make sure we aren't touching a non-existent +display controller and simplify the code. + +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 70 +++++++++------------------------- + drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 70 +++++++++------------------------- + drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 70 +++++++++------------------------- + 3 files changed, 51 insertions(+), 159 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +index ec2bd6a..f040de2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +@@ -3332,37 +3332,20 @@ static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev, + unsigned type, + enum amdgpu_interrupt_state state) + { +- u32 reg, reg_block; +- /* now deal with page flip IRQ */ +- switch (type) { +- case AMDGPU_PAGEFLIP_IRQ_D1: +- reg_block = CRTC0_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D2: +- reg_block = CRTC1_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D3: +- reg_block = CRTC2_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D4: +- reg_block = CRTC3_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D5: +- reg_block = CRTC4_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D6: +- reg_block = CRTC5_REGISTER_OFFSET; +- break; +- default: +- DRM_ERROR("invalid pageflip crtc %d\n", type); +- return -EINVAL; ++ u32 reg; ++ ++ if (type >= adev->mode_info.num_crtc) { ++ DRM_ERROR("invalid pageflip crtc %d\n", type); ++ return -EINVAL; + } + +- reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block); ++ reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); + if (state == AMDGPU_IRQ_STATE_DISABLE) +- WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); ++ WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], ++ reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + else +- WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); ++ WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], ++ reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + + return 0; + } +@@ -3371,7 +3354,6 @@ static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) + { +- int reg_block; + unsigned long flags; + unsigned crtc_id; + struct amdgpu_crtc *amdgpu_crtc; +@@ -3380,33 +3362,15 @@ static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev, + crtc_id = (entry->src_id - 8) >> 1; + amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; + +- /* ack the interrupt */ +- switch(crtc_id){ +- case AMDGPU_PAGEFLIP_IRQ_D1: +- reg_block = CRTC0_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D2: +- reg_block = CRTC1_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D3: +- reg_block = CRTC2_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D4: +- reg_block = CRTC3_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D5: +- reg_block = CRTC4_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D6: +- reg_block = CRTC5_REGISTER_OFFSET; +- break; +- default: +- DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); +- return -EINVAL; ++ if (crtc_id >= adev->mode_info.num_crtc) { ++ DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); ++ return -EINVAL; + } + +- if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) +- WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); ++ if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & ++ GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) ++ WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], ++ GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); + + /* IRQ could occur when in initial stage */ + if (amdgpu_crtc == NULL) +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +index 50cd429..f35d1aa 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +@@ -3308,37 +3308,20 @@ static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev, + unsigned type, + enum amdgpu_interrupt_state state) + { +- u32 reg, reg_block; +- /* now deal with page flip IRQ */ +- switch (type) { +- case AMDGPU_PAGEFLIP_IRQ_D1: +- reg_block = CRTC0_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D2: +- reg_block = CRTC1_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D3: +- reg_block = CRTC2_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D4: +- reg_block = CRTC3_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D5: +- reg_block = CRTC4_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D6: +- reg_block = CRTC5_REGISTER_OFFSET; +- break; +- default: +- DRM_ERROR("invalid pageflip crtc %d\n", type); +- return -EINVAL; ++ u32 reg; ++ ++ if (type >= adev->mode_info.num_crtc) { ++ DRM_ERROR("invalid pageflip crtc %d\n", type); ++ return -EINVAL; + } + +- reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block); ++ reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); + if (state == AMDGPU_IRQ_STATE_DISABLE) +- WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); ++ WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], ++ reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + else +- WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); ++ WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], ++ reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + + return 0; + } +@@ -3347,7 +3330,6 @@ static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) + { +- int reg_block; + unsigned long flags; + unsigned crtc_id; + struct amdgpu_crtc *amdgpu_crtc; +@@ -3356,33 +3338,15 @@ static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, + crtc_id = (entry->src_id - 8) >> 1; + amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; + +- /* ack the interrupt */ +- switch(crtc_id){ +- case AMDGPU_PAGEFLIP_IRQ_D1: +- reg_block = CRTC0_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D2: +- reg_block = CRTC1_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D3: +- reg_block = CRTC2_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D4: +- reg_block = CRTC3_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D5: +- reg_block = CRTC4_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D6: +- reg_block = CRTC5_REGISTER_OFFSET; +- break; +- default: +- DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); +- return -EINVAL; ++ if (crtc_id >= adev->mode_info.num_crtc) { ++ DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); ++ return -EINVAL; + } + +- if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) +- WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); ++ if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & ++ GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) ++ WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], ++ GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); + + /* IRQ could occur when in initial stage */ + if(amdgpu_crtc == NULL) +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +index 02f2100..0a0e8f0 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +@@ -3339,37 +3339,20 @@ static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, + unsigned type, + enum amdgpu_interrupt_state state) + { +- u32 reg, reg_block; +- /* now deal with page flip IRQ */ +- switch (type) { +- case AMDGPU_PAGEFLIP_IRQ_D1: +- reg_block = CRTC0_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D2: +- reg_block = CRTC1_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D3: +- reg_block = CRTC2_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D4: +- reg_block = CRTC3_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D5: +- reg_block = CRTC4_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D6: +- reg_block = CRTC5_REGISTER_OFFSET; +- break; +- default: +- DRM_ERROR("invalid pageflip crtc %d\n", type); +- return -EINVAL; ++ u32 reg; ++ ++ if (type >= adev->mode_info.num_crtc) { ++ DRM_ERROR("invalid pageflip crtc %d\n", type); ++ return -EINVAL; + } + +- reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block); ++ reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); + if (state == AMDGPU_IRQ_STATE_DISABLE) +- WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); ++ WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], ++ reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + else +- WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); ++ WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], ++ reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + + return 0; + } +@@ -3378,7 +3361,6 @@ static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) + { +- int reg_block; + unsigned long flags; + unsigned crtc_id; + struct amdgpu_crtc *amdgpu_crtc; +@@ -3387,33 +3369,15 @@ static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev, + crtc_id = (entry->src_id - 8) >> 1; + amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; + +- /* ack the interrupt */ +- switch(crtc_id){ +- case AMDGPU_PAGEFLIP_IRQ_D1: +- reg_block = CRTC0_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D2: +- reg_block = CRTC1_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D3: +- reg_block = CRTC2_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D4: +- reg_block = CRTC3_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D5: +- reg_block = CRTC4_REGISTER_OFFSET; +- break; +- case AMDGPU_PAGEFLIP_IRQ_D6: +- reg_block = CRTC5_REGISTER_OFFSET; +- break; +- default: +- DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); +- return -EINVAL; ++ if (crtc_id >= adev->mode_info.num_crtc) { ++ DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); ++ return -EINVAL; + } + +- if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) +- WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); ++ if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & ++ GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) ++ WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], ++ GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); + + /* IRQ could occur when in initial stage */ + if (amdgpu_crtc == NULL) +-- +1.9.1 + |