diff options
Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/files/1007-drm-amd-dal-remove-dead-code.patch')
| -rw-r--r-- | meta-amdfalconx86/recipes-kernel/linux/files/1007-drm-amd-dal-remove-dead-code.patch | 719 |
1 files changed, 719 insertions, 0 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1007-drm-amd-dal-remove-dead-code.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1007-drm-amd-dal-remove-dead-code.patch new file mode 100644 index 00000000..37cd6b17 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1007-drm-amd-dal-remove-dead-code.patch @@ -0,0 +1,719 @@ +From 31cf95fbd0163fa4a00f497d8bf40996701d8806 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Glisse?= <jglisse@redhat.com> +Date: Thu, 24 Mar 2016 14:23:37 +0100 +Subject: [PATCH 1007/1110] drm/amd/dal: remove dead code. +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Even more seriously ... + +Signed-off-by: Jérôme Glisse <jglisse@redhat.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/dal/dc/inc/core_types.h | 10 - + drivers/gpu/drm/amd/dal/include/dcs_types.h | 126 ------------- + drivers/gpu/drm/amd/dal/include/dmcu_types.h | 15 -- + drivers/gpu/drm/amd/dal/include/dpcd_defs.h | 209 --------------------- + .../drm/amd/dal/include/grph_object_ctrl_defs.h | 86 --------- + .../gpu/drm/amd/dal/include/link_service_types.h | 65 ------- + drivers/gpu/drm/amd/dal/include/video_csc_types.h | 10 - + .../gpu/drm/amd/dal/include/video_gamma_types.h | 8 - + 8 files changed, 529 deletions(-) + +diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h +index 9093e97..5994ad1 100644 +--- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h ++++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h +@@ -148,16 +148,6 @@ struct dpcd_caps { + int8_t branch_dev_name[6]; + }; + +-union dp_wa { +- struct { +- /* keep DP receiver powered up on DisplayOutput */ +- uint32_t KEEP_RECEIVER_POWERED:1; +- +- /* TODO: may add other member in.*/ +- } bits; +- uint32_t raw; +-}; +- + /* DP MST stream allocation (payload bandwidth number) */ + struct link_mst_stream_allocation { + /* DIG front */ +diff --git a/drivers/gpu/drm/amd/dal/include/dcs_types.h b/drivers/gpu/drm/amd/dal/include/dcs_types.h +index bccfd99..912310e 100644 +--- a/drivers/gpu/drm/amd/dal/include/dcs_types.h ++++ b/drivers/gpu/drm/amd/dal/include/dcs_types.h +@@ -61,45 +61,6 @@ enum edid_screen_aspect_ratio { + EDID_SCREEN_AR_4X5 + }; + +-union cv_smart_dongle_modes { +- uint8_t all; +- struct cv_smart_dongle_switches { +- uint8_t MODE_1080I:1; +- uint8_t MODE_720P:1; +- uint8_t MODE_540P:1; +- uint8_t MODE_480P:1; +- uint8_t MODE_480I:1; +- uint8_t MODE_16_9:1; +- } switches; +-}; +- +-union cea_speaker_allocation_data_block { +- struct { +- uint32_t FL_FR:1; +- uint32_t LFE:1; +- uint32_t FC:1; +- uint32_t RL_RR:1; +- uint32_t RC:1; +- uint32_t FLC_FRC:1; +- uint32_t RLC_RRC:1; +- } bits; +- uint32_t raw; +-}; +- +-union cea_video_capability_data_block { +- struct { +- uint8_t S_CE0:1; +- uint8_t S_CE1:1; +- uint8_t S_IT0:1; +- uint8_t S_IT1:1; +- uint8_t S_PT0:1; +- uint8_t S_PT1:1; +- uint8_t QS:1; +- uint8_t QY:1; +- } bits; +- uint8_t raw; +-}; +- + enum stereo_3d_multi_presence { + STEREO_3D_MULTI_NOT_PRESENT = 0, + STEREO_3D_MULTI_ALL_FORMATS, +@@ -131,47 +92,6 @@ enum dcs_interface_type { + INTERFACE_TYPE_EDP + }; + +- +-union panel_misc_info { +- struct { +- uint32_t H_CUT_OFF:1; +- uint32_t H_SYNC_POLARITY:1;/*0=Active High, 1=Active Low*/ +- uint32_t V_SYNC_POLARITY:1; /*0=Active High, 1=Active Low*/ +- uint32_t V_CUT_OFF:1; +- uint32_t H_REPLICATION_BY_2:1; +- uint32_t V_REPLICATION_BY_2:1; +- uint32_t COMPOSITE_SYNC:1; +- uint32_t INTERLACE:1; +- uint32_t DOUBLE_CLOCK:1; +- uint32_t RGB888:1; +- uint32_t GREY_LEVEL:2; +- uint32_t SPATIAL:1; +- uint32_t TEMPORAL:1; +- uint32_t API_ENABLED:1; +- } bits; +- uint32_t raw; +-}; +- +-union hdtv_mode_support { +- struct { +- uint32_t HDTV_SUPPORT_480I:1; +- uint32_t HDTV_SUPPORT_480P:1; +- uint32_t HDTV_SUPPORT_576I25:1; +- uint32_t HDTV_SUPPORT_576P50:1; +- uint32_t HDTV_SUPPORT_720P:1; +- uint32_t HDTV_SUPPORT_720P50:1; +- uint32_t HDTV_SUPPORT_1080I:1; +- uint32_t HDTV_SUPPORT_1080I25:1; +- uint32_t HDTV_SUPPORT_1080P:1; +- uint32_t HDTV_SUPPORT_1080P50:1; +- uint32_t HDTV_SUPPORT_1080P24:1; +- uint32_t HDTV_SUPPORT_1080P25:1; +- uint32_t HDTV_SUPPORT_1080P30:1; +- uint32_t HDTV_SUPPORT_16X9:1; +- } bits; +- uint32_t raw; +-}; +- + enum edid_retrieve_status { + EDID_RETRIEVE_SUCCESS = 0, + EDID_RETRIEVE_FAIL, +@@ -424,50 +344,4 @@ enum monitor_patch_type { + MONITOR_PATCH_TYPE_SINGLE_MODE_PACKED_PIXEL + }; + +-union dcs_monitor_patch_flags { +- struct { +- bool ERROR_CHECKSUM:1; +- bool HDTV_WITH_PURE_DFP_EDID:1; +- bool DO_NOT_USE_DETAILED_TIMING:1; +- bool DO_NOT_USE_RANGE_LIMITATION:1; +- bool EDID_EXTENTION_ERROR_CHECKSUM:1; +- bool TURN_OFF_DISPLAY_BEFORE_MODE_CHANGE:1; +- bool RESTRICT_VESA_MODE_TIMING:1; +- bool DO_NOT_USE_EDID_MAX_PIX_CLK:1; +- bool VENDOR_0:1; +- bool RANDOM_CRT:1;/* 10 bits used including this one-*/ +- bool VENDOR_1:1; +- bool LIMIT_PANEL_SUPPORT_RGB_ONLY:1; +- bool PACKED_PIXEL_FORMAT:1; +- bool LARGE_PANEL:1; +- bool STEREO_SUPPORT:1; +- bool DUAL_EDID_PANEL:1; +- bool IGNORE_19X12_STD_TIMING:1; +- bool MULTIPLE_PACKED_TYPE:1; +- bool RESET_TX_ON_DISPLAY_POWER_ON:1; +- bool ALLOW_ONLY_CE_MODE:1;/* 20 bits used including this one*/ +- bool RESTRICT_PROT_DUAL_LINK_DVI:1; +- bool FORCE_LINK_RATE:1; +- bool DELAY_AFTER_DP_RECEIVER_POWER_UP:1; +- bool KEEP_DP_RECEIVER_POWERED:1; +- bool DELAY_BEFORE_READ_EDID:1; +- bool DELAY_AFTER_PIXEL_FORMAT_CHANGE:1; +- bool INCREASE_DEFER_WRITE_RETRY_I2C_OVER_AUX:1; +- bool NO_DEFAULT_TIMINGS:1; +- bool ADD_CEA861_DETAILED_TIMING_VIC16:1; +- bool ADD_CEA861_DETAILED_TIMING_VIC31:1; /* 30 bits*/ +- bool DELAY_BEFORE_UNMUTE:1; +- bool RETRY_LINK_TRAINING_ON_FAILURE:1; +- bool ALLOW_AUX_WHEN_HPD_LOW:1; +- bool TILED_DISPLAY:1; +- bool DISABLE_PSR_ENTRY_ABORT:1; +- bool INTERMITTENT_EDID_ERROR:1;/* 36 bits total*/ +- bool VID_STREAM_DIFFER_TO_SYNC:1;/* 37 bits total*/ +- bool EXTRA_DELAY_ON_DISCONNECT:1;/* 38 bits total*/ +- bool DELAY_AFTER_DISABLE_BACKLIGHT_DFS_BYPASS:1;/* 39 bits total*/ +- } flags; +- uint64_t raw; +-}; +- + #endif /* __DAL_DCS_TYPES_H__ */ +- +diff --git a/drivers/gpu/drm/amd/dal/include/dmcu_types.h b/drivers/gpu/drm/amd/dal/include/dmcu_types.h +index 00f9fa4..b74bb5b 100644 +--- a/drivers/gpu/drm/amd/dal/include/dmcu_types.h ++++ b/drivers/gpu/drm/amd/dal/include/dmcu_types.h +@@ -129,21 +129,6 @@ struct dmcu_context { + uint32_t vsync_rate_hz; + }; + +-union dmcu_psr_level { +- struct { +- bool SKIP_CRC:1; +- bool SKIP_DP_VID_STREAM_DISABLE:1; +- bool SKIP_PHY_POWER_DOWN:1; +- bool SKIP_AUX_ACK_CHECK:1; +- bool SKIP_CRTC_DISABLE:1; +- bool SKIP_AUX_RFB_CAPTURE_CHECK:1; +- bool SKIP_SMU_NOTIFICATION:1; +- bool SKIP_AUTO_STATE_ADVANCE:1; +- bool DISABLE_PSR_ENTRY_ABORT:1; +- } bits; +- uint32_t u32all; +-}; +- + enum varibright_command { + VARIBRIGHT_CMD_SET_VB_LEVEL = 0, + VARIBRIGHT_CMD_USER_ENABLE, +diff --git a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h +index e251cff..27b7aee 100644 +--- a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h ++++ b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h +@@ -414,16 +414,6 @@ union mstm_cap { + uint8_t raw; + }; + +-union mstm_cntl { +- struct { +- uint8_t MST_EN:1; +- uint8_t UP_REQ_EN:1; +- uint8_t UPSTREAM_IS_SRC:1; +- uint8_t RESERVED:5; +- } bits; +- uint8_t raw; +-}; +- + union lane_count_set { + struct { + uint8_t LANE_COUNT_SET:5; +@@ -434,44 +424,6 @@ union lane_count_set { + uint8_t raw; + }; + +-/* for DPCD_ADDRESS_I2C_SPEED_CNTL_CAP +- * and DPCD_ADDRESS_I2C_SPEED_CNTL +- */ +-union i2c_speed { +- struct { +- uint8_t _1KBPS:1; +- uint8_t _5KBPS:1; +- uint8_t _10KBPS:1; +- uint8_t _100KBPS:1; +- uint8_t _400KBPS:1; +- uint8_t _1MBPS:1; +- uint8_t reserved:2; +- } bits; +- uint8_t raw; +-}; +- +-union payload_table_update_status { +- struct { +- uint8_t VC_PAYLOAD_TABLE_UPDATED:1; +- uint8_t ACT_HANDLED:1; +- } bits; +- uint8_t raw; +-}; +- +-union device_irq_esi_0 { +- struct { +- uint8_t REMOTE_CONTROL_CMD_PENDING:1; +- uint8_t AUTOMATED_TEST_REQUEST:1; +- uint8_t CP_IRQ:1; +- uint8_t MCCS_IRQ:1; +- uint8_t DOWN_REP_MSG_RDY:1; +- uint8_t UP_REQ_MSG_RDY:1; +- uint8_t SINK_SPECIFIC_IRQ:1; +- uint8_t RESERVED:1; +- } bits; +- uint8_t raw; +-}; +- + union lane_status { + struct { + uint8_t CR_DONE_0:1; +@@ -500,17 +452,6 @@ union device_service_irq { + uint8_t raw; + }; + +-union downstream_port { +- struct { +- uint8_t PRESENT:1; +- uint8_t TYPE:2; +- uint8_t FORMAT_CONV:1; +- uint8_t DETAILED_CAPS:1; +- uint8_t RESERVED:3; +- } bits; +- uint8_t raw; +-}; +- + union sink_count { + struct { + uint8_t SINK_COUNT:6; +@@ -540,74 +481,6 @@ union lane_adjust { + uint8_t raw; + }; + +-/* Automated test structures */ +-union test_request { +- struct { +- uint8_t LINK_TRAINING:1; +- uint8_t LINK_TEST_PATTERN:1; +- uint8_t EDID_READ:1; +- uint8_t PHY_TEST_PATTERN:1; +- uint8_t AUDIO_TEST_PATTERN:1; +- uint8_t AUDIO_TEST_NO_VIDEO:1; +- uint8_t RESERVED:1; +- uint8_t TEST_STEREO_3D:1; +- } bits; +- uint8_t raw; +-}; +- +-union test_response { +- struct { +- uint8_t ACK:1; +- uint8_t NO_ACK:1; +- uint8_t RESERVED:6; +- } bits; +- uint8_t raw; +-}; +- +-union link_test_pattern { +- struct { +- uint8_t PATTERN:2;/*DpcdLinkTestPatterns*/ +- uint8_t RESERVED:6; +- } bits; +- uint8_t raw; +-}; +- +-union test_misc { +- struct dpcd_test_misc_bits { +- uint8_t SYNC_CLOCK:1; +- uint8_t CLR_FORMAT:2;/*DpcdTestColorFormat*/ +- uint8_t DYN_RANGE:1;/*DpcdTestDynRange*/ +- uint8_t YCBCR:1;/*DpcdTestYCbCrStandard*/ +- uint8_t BPC:3;/*DpcdTestBitDepth*/ +- } bits; +- uint8_t raw; +-}; +- +-union phy_test_pattern { +- struct { +- /* This field is 2 bits for DP1.1 and 3 bits for DP1.2.*/ +- uint8_t PATTERN:3; +- uint8_t RESERVED:5;/* BY spec, bit7:2 is 0 for DP1.1.*/ +- } bits; +- uint8_t raw; +-}; +- +-union audio_test_mode { +- struct { +- uint8_t SAMPLING_RATE:4; +- uint8_t CHANNEL_COUNT:4; +- } bits; +- uint8_t raw; +-}; +- +-union audio_test_pattern_period { +- struct { +- uint8_t PATTERN_PERIOD:4; +- uint8_t RESERVED:4; +- } bits; +- uint8_t raw; +-}; +- + union dpcd_training_pattern { + struct { + uint8_t TRAINING_PATTERN_SET:4; +@@ -641,68 +514,8 @@ union dpcd_training_lane { + post cursor 2 level of Training Pattern 2 or 3*/ + /* The DPCD addresses are 0x10F (TRAINING_LANE0_1_SET2) + and 0x110 (TRAINING_LANE2_3_SET2)*/ +-union dpcd_training_lane_set2 { +- struct { +- uint8_t POST_CURSOR2_SET:2; +- uint8_t MAX_POST_CURSOR2_REACHED:1; +- uint8_t RESERVED:1; +- } bits; +- uint8_t raw; +-}; +- +-union dpcd_psr_configuration { +- struct { +- uint8_t ENABLE:1; +- uint8_t TRANSMITTER_ACTIVE_IN_PSR:1; +- uint8_t CRC_VERIFICATION:1; +- uint8_t FRAME_CAPTURE_INDICATION:1; +- uint8_t LINE_CAPTURE_INDICATION:1; +- uint8_t IRQ_HPD_WITH_CRC_ERROR:1; +- uint8_t RESERVED:2; +- } bits; +- uint8_t raw; +-}; +- +-union psr_error_status { +- struct { +- uint8_t LINK_CRC_ERROR:1; +- uint8_t RFB_STORAGE_ERROR:1; +- uint8_t RESERVED:6; +- } bits; +- uint8_t raw; +-}; +- +-union psr_event_status_ind { +- struct { +- uint8_t SINK_PSR_CAP_CHANGE:1; +- uint8_t RESERVED:7; +- } bits; +- uint8_t raw; +-}; +- +-union psr_sink_psr_status { +- struct { +- uint8_t SINK_SELF_REFRESH_STATUS:3; +- uint8_t RESERVED:5; +- } bits; +- uint8_t raw; +-}; + + /* EDP related 0x701 */ +-union edp_generial_cap1 { +- struct { +- uint8_t TCON_BACKLIGHT_ADJUSTMENT_CAPABLE:1; +- uint8_t BACKLIGHT_PIN_ENABLE_CAPABLE:1; +- uint8_t BACKLIGHT_AUX_ENABLE_CAPABLE:1; +- uint8_t PANEL_SELFTEST_PIN_ENABLE_CAPABLE:1; +- uint8_t BACKLIGHT_SELFTEST_AUX_ENABLE_CAPABLE:1; +- uint8_t FRC_ENABLE_CAPABLE:1; +- uint8_t COLOR_ENGINE_CAPABLE:1; +- /*bit 7, pane can be controlled by 0x600*/ +- uint8_t SET_POWER_CAPABLE:1; +- } bits; +- uint8_t raw; +-}; + + /* TMDS-converter related */ + union dwnstream_port_caps_byte0 { +@@ -763,19 +576,6 @@ union dwnstream_port_caps_byte3_hdmi { + + /*4-byte structure for detailed capabilities of a down-stream port + (DP-to-TMDS converter).*/ +-union dwnstream_portx_caps { +- struct { +- union dwnstream_port_caps_byte0 byte0; +- uint8_t max_tmds_clk;/* byte1 */ +- union dwnstream_port_caps_byte2 byte2; +- +- union { +- union dwnstream_port_caps_byte3_dvi byte_dvi; +- union dwnstream_port_caps_byte3_hdmi byte_hdmi; +- } byte3; +- } bytes; +- uint8_t raw[4]; +-}; + + union sink_status { + struct { +@@ -862,15 +662,6 @@ union edp_configuration_cap { + uint8_t raw; + }; + +-union psr_capabilities { +- struct { +- uint8_t EXIT_LT_NOT_REQ:1; +- uint8_t RFB_SETUP_TIME:3; +- uint8_t RESERVED:4; +- } bits; +- uint8_t raw; +-}; +- + union training_aux_rd_interval { + struct { + uint8_t TRAINIG_AUX_RD_INTERVAL:7; +diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h +index 11b1b99..50e3f0a 100644 +--- a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h ++++ b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h +@@ -189,23 +189,6 @@ struct firmware_info { + uint8_t remote_display_config; + }; + +-/* direct HW (mmBIOS_SCRATCH_2) translation! */ +-union tv_standard_support { +- uint8_t u_all; +- struct { +- bool TV_SUPPORT_NTSC:1; +- bool TV_SUPPORT_NTSCJ:1; +- +- bool TV_SUPPORT_PAL:1; +- bool TV_SUPPORT_PALM:1; +- bool TV_SUPPORT_PALCN:1; +- bool TV_SUPPORT_PALN:1; +- bool TV_SUPPORT_PAL60:1; +- +- bool TV_SUPPORT_SECAM:1; +- } bits; +-}; +- + struct step_and_delay_info { + uint32_t step; + uint32_t delay; +@@ -406,47 +389,6 @@ struct bios_event_info { + bool backlight_changed; + }; + +-union stereo_3d_support { +- struct { +- /* HW can alter left and right image sequentially */ +- uint32_t FRAME_ALTERNATE:1; +- /* Frame Alternate + HW can integrate stereosync +- signal into TMDS stream */ +- uint32_t DVI_FRAME_ALT:1; +- /* Frame Alternate + HW can integrate stereosync +- signal into DP stream */ +- uint32_t DISPLAY_PORT_FRAME_ALT:1; +- /* Frame Alternate + HW can drive stereosync signal +- on separate line */ +- uint32_t SIDEBAND_FRAME_ALT:1; +- /* SW allowed to pack left and right image into single frame. +- Used for HDMI only, DP has it's own flags. */ +- uint32_t SW_FRAME_PACK:1; +- /* HW can pack left and right image into single HDMI frame */ +- uint32_t PROGRESSIVE_FRAME_PACK:1; +- /* HW can pack left and right interlaced images into +- single HDMI frame */ +- uint32_t INTERLACE_FRAME_PACK:1; +- /* HW can pack left and right images into single DP frame */ +- uint32_t DISPLAY_PORT_FRAME_PACK:1; +- /* SW can pack left and right images into single DP frame */ +- uint32_t DISPLAY_PORT_SW_FRAME_PACK:1; +- /* HW can mix left and right images into single image */ +- uint32_t INTERLEAVE:1; +- /* HW can mix left and right interlaced images +- into single image */ +- uint32_t INTERLACE_INTERLEAVE:1; +- /* Allow display-based formats (whatever supported) +- in WS stereo mode */ +- uint32_t DISPLAY_3DIN_WS_MODE:1; +- /* Side-by-side, packed by application/driver into 2D frame */ +- uint32_t SIDE_BY_SIDE_SW_PACKED:1; +- /* Top-and-bottom, packed by application/driver into 2D frame */ +- uint32_t TOP_AND_BOTTOM_SW_PACKED:1; +- } bits; +- uint32_t u_all; +-}; +- + /* Bitvector and bitfields of possible optimizations + #IMPORTANT# Keep bitfields match bitvector! */ + enum optimization_feature { +@@ -463,37 +405,9 @@ enum optimization_feature { + OF_SKIP_POWER_DOWN_INACTIVE_ENCODER = 0x80 + }; + +-union optimization_flags { +- struct { +- /* Don't do HW programming if panels were enabled by VBIOS */ +- uint32_t SKIP_HW_PROGRAMMING_ON_ENABLED_EMBEDDED_DISPLAY:1; +- uint32_t SKIP_RESET_OF_ALL_HW_ON_S3RESUME:1; +- uint32_t SKIP_HW_RESET_OF_EMBEDDED_DISPLAY_ON_S3RESUME:1; +- uint32_t SKIP_POWER_UP_VBIOS_ENABLED_ENCODER:1; +- /* Do not turn off VCC while powering down on boot or resume */ +- uint32_t KEEP_VCC_DURING_POWER_DOWN_ON_BOOT_OR_RESUME:1; +- /* Do not turn off VCC while performing SetMode */ +- uint32_t KEEP_VCC_DURING_SET_MODE:1; +- uint32_t DO_NOT_WAIT_FOR_HPD_LOW:1; +- } bits; +- uint32_t u_all; +-}; +- + /* Bitvector and bitfields of performance measurements + #IMPORTANT# Keep bitfields match bitvector! */ + +-union perf_measure_flags { +- struct { +- uint32_t ADAPTER_POWER_STATE:1; +- uint32_t DISPLAY_POWER_STATE:1; +- uint32_t SET_MODE_SEQ:1; +- uint32_t DETECT_AT_RESUME:1; +- uint32_t MEMORY_READ_CONTROL:1; +- +- } bits; +- uint32_t u_all; +-}; +- + enum { + PERF_MEASURE_POWERCODE_OFFSET = 0x0, + PERF_MEASURE_POWER_CODE_MASK = 0xFF, +diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h +index a14c4af..5dd75a3 100644 +--- a/drivers/gpu/drm/amd/dal/include/link_service_types.h ++++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h +@@ -82,46 +82,6 @@ enum edp_revision { + EDP_REVISION_13 = 0x02 + }; + +-/* DPCD_ADDR_DOWNSTREAM_PORT_PRESENT register value */ +-union dpcd_downstream_port { +- struct { +-#if defined(LITTLEENDIAN_CPU) +- uint8_t PRESENT:1; +- uint8_t TYPE:2; +- uint8_t FORMAT_CONV:1; +- uint8_t RESERVED:4; +-#elif defined(BIGENDIAN_CPU) +- uint8_t RESERVED:4; +- uint8_t FORMAT_CONV:1; +- uint8_t TYPE:2; +- uint8_t PRESENT:1; +-#else +- #error ARCH not defined! +-#endif +- } bits; +- +- uint8_t raw; +-}; +- +-/* DPCD_ADDR_SINK_COUNT register value */ +-union dpcd_sink_count { +- struct { +-#if defined(LITTLEENDIAN_CPU) +- uint8_t SINK_COUNT:6; +- uint8_t CP_READY:1; +- uint8_t RESERVED:1; +-#elif defined(BIGENDIAN_CPU) +- uint8_t RESERVED:1; +- uint8_t CP_READY:1; +- uint8_t SINK_COUNT:6; +-#else +- #error ARCH not defined! +-#endif +- } bits; +- +- uint8_t raw; +-}; +- + enum { + LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/ + }; +@@ -244,31 +204,6 @@ union dpcd_training_lane_set { + uint8_t raw; + }; + +-/* DPCD_ADDR_TRAINING_LANEx_SET2 registers value - since DP 1.2 */ +-union dpcd_training_lanes_set2 { +- struct { +-#if defined(LITTLEENDIAN_CPU) +- uint8_t LANE0_POST_CURSOR2_SET:2; +- uint8_t LANE0_MAX_POST_CURSOR2_REACHED:1; +- uint8_t LANE0_RESERVED:1; +- uint8_t LANE1_POST_CURSOR2_SET:2; +- uint8_t LANE1_MAX_POST_CURSOR2_REACHED:1; +- uint8_t LANE1_RESERVED:1; +-#elif defined(BIGENDIAN_CPU) +- uint8_t LANE1_RESERVED:1; +- uint8_t LANE1_MAX_POST_CURSOR2_REACHED:1; +- uint8_t LANE1_POST_CURSOR2_SET:2; +- uint8_t LANE0_RESERVED:1; +- uint8_t LANE0_MAX_POST_CURSOR2_REACHED:1; +- uint8_t LANE0_POST_CURSOR2_SET:2; +-#else +- #error ARCH not defined! +-#endif +- } bits; +- +- uint8_t raw; +-}; +- + /** + * @brief represent the 16 byte + * global unique identifier +diff --git a/drivers/gpu/drm/amd/dal/include/video_csc_types.h b/drivers/gpu/drm/amd/dal/include/video_csc_types.h +index 96b4ac9..258e5ad 100644 +--- a/drivers/gpu/drm/amd/dal/include/video_csc_types.h ++++ b/drivers/gpu/drm/amd/dal/include/video_csc_types.h +@@ -32,14 +32,4 @@ + #define MAXTRIX_SIZE TEMPERATURE_MAXTRIX_SIZE + #define MAXTRIX_SIZE_WITH_OFFSET 12 + +-/* overlay adjustment input */ +-union ovl_csc_flag { +- uint32_t u_all; +- struct { +- uint32_t CONFIG_IS_CHANGED:1; +- uint32_t RESERVED:31; +- } bits; +-}; +- +- + #endif +diff --git a/drivers/gpu/drm/amd/dal/include/video_gamma_types.h b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h +index 1e249ac..5c70a75 100644 +--- a/drivers/gpu/drm/amd/dal/include/video_gamma_types.h ++++ b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h +@@ -29,12 +29,4 @@ + #include "set_mode_types.h" + #include "gamma_types.h" + +-union video_gamma_flag { +- struct { +- uint32_t CONFIG_IS_CHANGED:1; +- uint32_t RESERVED:31; +- } bits; +- uint32_t u_all; +-}; +- + #endif +-- +2.7.4 + |