diff options
Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/files/0998-drm-amd-dal-fix-dce112-dp-clock-switching.patch')
| -rw-r--r-- | meta-amdfalconx86/recipes-kernel/linux/files/0998-drm-amd-dal-fix-dce112-dp-clock-switching.patch | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0998-drm-amd-dal-fix-dce112-dp-clock-switching.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0998-drm-amd-dal-fix-dce112-dp-clock-switching.patch new file mode 100644 index 00000000..87c102fb --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/0998-drm-amd-dal-fix-dce112-dp-clock-switching.patch @@ -0,0 +1,69 @@ +From a4e0f90b01fe5c4d25a62da00692da898477deac Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Thu, 31 Mar 2016 17:56:46 -0400 +Subject: [PATCH 0998/1110] drm/amd/dal: fix dce112 dp clock switching + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 2 +- + drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c | 17 +++++++++++------ + 2 files changed, 12 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c +index df52740..47f75ef 100644 +--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c +@@ -339,7 +339,7 @@ static void dce110_crtc_switch_to_clk_src( + DP_DTO0_ENABLE); + + set_reg_field_value(pixel_rate_cntl_value, +- clk_src->id - 1, ++ clk_src->id - CLOCK_SOURCE_ID_PLL0, + CRTC0_PIXEL_RATE_CNTL, + CRTC0_PIXEL_RATE_SOURCE); + } +diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c +index b887764..931e47e 100644 +--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c +@@ -231,8 +231,11 @@ static void dce112_crtc_switch_to_clk_src( + struct clock_source *clk_src, uint8_t crtc_inst) + { + uint32_t pixel_rate_cntl_value; +- uint32_t addr; ++ uint32_t phypll_pixel_rate_cntl_value = 0; ++ uint32_t addr, phypll_addr; + ++ phypll_addr = mmCRTC0_PHYPLL_PIXEL_RATE_CNTL + crtc_inst * ++ (mmCRTC1_PHYPLL_PIXEL_RATE_CNTL - mmCRTC0_PHYPLL_PIXEL_RATE_CNTL); + addr = mmCRTC0_PIXEL_RATE_CNTL + crtc_inst * + (mmCRTC1_PIXEL_RATE_CNTL - mmCRTC0_PIXEL_RATE_CNTL); + +@@ -242,15 +245,17 @@ static void dce112_crtc_switch_to_clk_src( + set_reg_field_value(pixel_rate_cntl_value, 1, + CRTC0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE); + else { +- set_reg_field_value(pixel_rate_cntl_value, +- 0, +- CRTC0_PIXEL_RATE_CNTL, +- DP_DTO0_ENABLE); + + set_reg_field_value(pixel_rate_cntl_value, +- clk_src->id - 1, ++ clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0, + CRTC0_PIXEL_RATE_CNTL, + CRTC0_PIXEL_RATE_SOURCE); ++ ++ set_reg_field_value(phypll_pixel_rate_cntl_value, ++ clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0, ++ CRTC0_PHYPLL_PIXEL_RATE_CNTL, ++ CRTC0_PHYPLL_PIXEL_RATE_SOURCE); ++ dm_write_reg(clk_src->ctx, phypll_addr, phypll_pixel_rate_cntl_value); + } + dm_write_reg(clk_src->ctx, addr, pixel_rate_cntl_value); + } +-- +2.7.4 + |