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Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/files/0786-drm-amd-dal-Consolidate-safe-and-generic-watermark-p.patch')
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/0786-drm-amd-dal-Consolidate-safe-and-generic-watermark-p.patch261
1 files changed, 261 insertions, 0 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0786-drm-amd-dal-Consolidate-safe-and-generic-watermark-p.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0786-drm-amd-dal-Consolidate-safe-and-generic-watermark-p.patch
new file mode 100644
index 00000000..006b9bd8
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0786-drm-amd-dal-Consolidate-safe-and-generic-watermark-p.patch
@@ -0,0 +1,261 @@
+From dfb0581b9d72f656d93249b3e92b39b719410139 Mon Sep 17 00:00:00 2001
+From: David Rokhvarg <David.Rokhvarg@amd.com>
+Date: Tue, 9 Feb 2016 14:28:31 -0500
+Subject: [PATCH 0786/1110] drm/amd/dal: Consolidate "safe" and "generic"
+ watermark programming.
+
+Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
+Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
+---
+ .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 64 ++++++++++++++++------
+ .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 24 +-------
+ .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h | 12 +---
+ drivers/gpu/drm/amd/dal/dc/inc/mem_input.h | 7 +--
+ 4 files changed, 52 insertions(+), 55 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+index 43840c1..a815a6d 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+@@ -102,6 +102,9 @@ static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
+ (reg + reg_offsets[id].crtc)
+
+
++#define MAX_WATERMARK 0xFFFF
++#define SAFE_NBP_MARK 0x7FFF
++
+ /*******************************************************************************
+ * Private definitions
+ ******************************************************************************/
+@@ -1129,41 +1132,64 @@ static void set_display_clock(struct validate_context *context)
+ /* TODO: Start GTC counter */
+ }
+
++static uint32_t compute_pstate_blackout_duration(
++ const struct dc *dc,
++ const struct core_stream *stream)
++{
++ uint32_t total_dest_line_time_ns;
++ uint32_t pstate_blackout_duration_ns;
++
++ pstate_blackout_duration_ns = 1000 *
++ dc->bw_vbios.blackout_duration.value >> 24;
++
++ total_dest_line_time_ns = 1000000UL *
++ stream->public.timing.h_total /
++ stream->public.timing.pix_clk_khz +
++ pstate_blackout_duration_ns;
++
++ return total_dest_line_time_ns;
++}
++
+ static void set_displaymarks(
+- const struct dc *dc, struct validate_context *context)
++ const struct dc *dc,
++ struct validate_context *context)
+ {
+ uint8_t i, j;
+ uint8_t total_streams = 0;
+ uint8_t target_count = context->target_count;
++ uint32_t pstate_blackout_duration_ns;
+
+ for (i = 0; i < target_count; i++) {
+- struct core_target *target = context->targets[i];
++ const struct core_target *target = context->targets[i];
+
+ for (j = 0; j < target->public.stream_count; j++) {
+- struct core_stream *stream =
++ const struct core_stream *stream =
+ DC_STREAM_TO_CORE(target->public.streams[j]);
+
++ pstate_blackout_duration_ns =
++ compute_pstate_blackout_duration(dc, stream);
++
+ stream->mi->funcs->mem_input_program_display_marks(
+ stream->mi,
+ context->bw_results
+- .nbp_state_change_wm_ns[total_streams],
++ .nbp_state_change_wm_ns[total_streams],
+ context->bw_results
+ .stutter_exit_wm_ns[total_streams],
+- context->bw_results
+- .urgent_wm_ns[total_streams],
+- stream->public.timing.h_total,
+- stream->public.timing.pix_clk_khz,
+- 1000 * dc->bw_vbios.blackout_duration
+- .value >> 24);
++ context->bw_results.
++ urgent_wm_ns[total_streams],
++ pstate_blackout_duration_ns);
++
+ total_streams++;
+- }
+- }
++ } /* for ()*/
++ } /* for() */
+ }
+
+-static void set_safe_displaymarks(struct validate_context *context)
++static void set_safe_displaymarks(const struct dc *dc, struct validate_context *context)
+ {
+ uint8_t i, j;
+ uint8_t target_count = context->target_count;
++ struct bw_watermarks max_marks = { MAX_WATERMARK, MAX_WATERMARK };
++ struct bw_watermarks nbp_marks = { SAFE_NBP_MARK, SAFE_NBP_MARK };
+
+ for (i = 0; i < target_count; i++) {
+ struct core_target *target = context->targets[i];
+@@ -1172,15 +1198,19 @@ static void set_safe_displaymarks(struct validate_context *context)
+ struct core_stream *stream =
+ DC_STREAM_TO_CORE(target->public.streams[j]);
+
+- stream->mi->funcs->mem_input_program_safe_display_marks(
+- stream->mi);
++ stream->mi->funcs->mem_input_program_display_marks(
++ stream->mi,
++ nbp_marks,
++ max_marks,
++ max_marks,
++ MAX_WATERMARK);
+ }
+ }
+ }
+
+ static void program_bw(struct dc *dc, struct validate_context *context)
+ {
+- set_safe_displaymarks(context);
++ set_safe_displaymarks(dc, context);
+ /*TODO: when pplib works*/
+ /*dc_set_clocks_and_clock_state(context);*/
+
+@@ -1252,7 +1282,7 @@ static enum dc_status apply_ctx_to_hw(
+ PIPE_GATING_CONTROL_DISABLE);
+ }
+
+- set_safe_displaymarks(context);
++ set_safe_displaymarks(dc, context);
+ /*TODO: when pplib works*/
+ /*dc_set_clocks_and_clock_state(context);*/
+
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
+index b718ac1..f640552 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
+@@ -36,8 +36,6 @@
+
+ #include "dce110_mem_input.h"
+
+-#define MAX_WATERMARK 0xFFFF
+-#define SAFE_NBP_MARK 0x7FFF
+
+ #define DCP_REG(reg) (reg + mem_input110->offsets.dcp)
+ #define DMIF_REG(reg) (reg + mem_input110->offsets.dmif)
+@@ -677,40 +675,26 @@ static void program_nbp_watermark(
+ dm_write_reg(ctx, addr, value);
+ }
+
+-void dce110_mem_input_program_safe_display_marks(struct mem_input *mi)
+-{
+- struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mi);
+- struct bw_watermarks max_marks = { MAX_WATERMARK, MAX_WATERMARK };
+- struct bw_watermarks nbp_marks = { SAFE_NBP_MARK, SAFE_NBP_MARK };
+-
+- program_urgency_watermark(
+- mi->ctx, bm_dce110->offsets.dmif, max_marks, MAX_WATERMARK);
+- program_stutter_watermark(mi->ctx, bm_dce110->offsets.dmif, max_marks);
+- program_nbp_watermark(mi->ctx, bm_dce110->offsets.dmif, nbp_marks);
+-}
+-
+ void dce110_mem_input_program_display_marks(
+ struct mem_input *mem_input,
+ struct bw_watermarks nbp,
+ struct bw_watermarks stutter,
+ struct bw_watermarks urgent,
+- uint32_t h_total,
+- uint32_t pixel_clk_in_khz,
+- uint32_t pstate_blackout_duration_ns)
++ uint32_t total_dest_line_time_ns)
+ {
+ struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mem_input);
+- uint32_t total_dest_line_time_ns = 1000000UL * h_total
+- / pixel_clk_in_khz + pstate_blackout_duration_ns;
+
+ program_urgency_watermark(
+ mem_input->ctx,
+ bm_dce110->offsets.dmif,
+ urgent,
+ total_dest_line_time_ns);
++
+ program_nbp_watermark(
+ mem_input->ctx,
+ bm_dce110->offsets.dmif,
+ nbp);
++
+ program_stutter_watermark(
+ mem_input->ctx,
+ bm_dce110->offsets.dmif,
+@@ -930,8 +914,6 @@ void dce110_free_mem_input(
+ }
+
+ static struct mem_input_funcs dce110_mem_input_funcs = {
+- .mem_input_program_safe_display_marks =
+- dce110_mem_input_program_safe_display_marks,
+ .mem_input_program_display_marks =
+ dce110_mem_input_program_display_marks,
+ .allocate_mem_input = dce110_allocate_mem_input,
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
+index 232d7fb..a0db7aa 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
+@@ -51,14 +51,6 @@ bool dce110_mem_input_construct(
+ /*
+ * dce110_mem_input_program_display_marks
+ *
+- * This function will program nbp stutter and urgency watermarks to maximum
+- * safe values
+- */
+-void dce110_mem_input_program_safe_display_marks(struct mem_input *mi);
+-
+-/*
+- * dce110_mem_input_program_display_marks
+- *
+ * This function will program nbp stutter and urgency watermarks to minimum
+ * allowable values
+ */
+@@ -67,9 +59,7 @@ void dce110_mem_input_program_display_marks(
+ struct bw_watermarks nbp,
+ struct bw_watermarks stutter,
+ struct bw_watermarks urgent,
+- uint32_t h_total,
+- uint32_t pixel_clk_in_khz,
+- uint32_t pstate_blackout_duration_ns);
++ uint32_t total_dest_line_time_ns);
+
+ /*
+ * dce110_allocate_mem_input
+diff --git a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
+index 747e5dc..9cd9905 100644
+--- a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
++++ b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
+@@ -35,17 +35,12 @@ struct mem_input {
+ };
+
+ struct mem_input_funcs {
+- void (*mem_input_program_safe_display_marks)(
+- struct mem_input *mi);
+-
+ void (*mem_input_program_display_marks)(
+ struct mem_input *mem_input,
+ struct bw_watermarks nbp,
+ struct bw_watermarks stutter,
+ struct bw_watermarks urgent,
+- uint32_t h_total,
+- uint32_t pixel_clk_in_khz,
+- uint32_t pstate_blackout_duration_ns);
++ uint32_t total_dest_line_time_ns);
+
+ void (*allocate_mem_input)(
+ struct mem_input *mem_input,
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-04 00:32:10 +0000