diff options
Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/files/0046-drm-amd-powerplay-add-Carrizo-dpm-support.patch')
| -rw-r--r-- | meta-amdfalconx86/recipes-kernel/linux/files/0046-drm-amd-powerplay-add-Carrizo-dpm-support.patch | 1283 |
1 files changed, 1283 insertions, 0 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0046-drm-amd-powerplay-add-Carrizo-dpm-support.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0046-drm-amd-powerplay-add-Carrizo-dpm-support.patch new file mode 100644 index 00000000..317c6730 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/0046-drm-amd-powerplay-add-Carrizo-dpm-support.patch @@ -0,0 +1,1283 @@ +From bab619f2322c11d323bd5dd451cff5c7d7db49fc Mon Sep 17 00:00:00 2001 +From: Jammy Zhou <Jammy.Zhou@amd.com> +Date: Wed, 22 Jul 2015 10:41:30 +0800 +Subject: [PATCH 0046/1110] drm/amd/powerplay: add Carrizo dpm support + +This patch enables basic DPM support for Carrizo. +DPM handles dynamic clock and voltage scaling. + +v3: delete peci sub-module +v2: use cgs interface directly + correct define SMU_EnabledFeatureScoreboard_SclkDpmOn + +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +- + drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 898 +++++++++++++++++++++++++ + drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h | 309 +++++++++ + drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 6 +- + 4 files changed, 1212 insertions(+), 3 deletions(-) + create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c + create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +index ef529e0..22d383e 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +@@ -3,7 +3,7 @@ + # It provides the hardware management services for the driver. + + HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \ +- hardwaremanager.o pp_acpi.o ++ hardwaremanager.o pp_acpi.o cz_hwmgr.o + + AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +new file mode 100644 +index 0000000..0c49505 +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +@@ -0,0 +1,898 @@ ++/* ++ * Copyright 2015 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#include <linux/types.h> ++#include <linux/kernel.h> ++#include <linux/slab.h> ++#include "atom-types.h" ++#include "atombios.h" ++#include "processpptables.h" ++#include "cgs_common.h" ++#include "smu/smu_8_0_d.h" ++#include "smumgr.h" ++#include "hwmgr.h" ++#include "hardwaremanager.h" ++#include "cz_ppsmc.h" ++#include "cz_hwmgr.h" ++#include "power_state.h" ++ ++static const unsigned long PhwCz_Magic = (unsigned long) PHM_Cz_Magic; ++ ++static struct cz_power_state *cast_PhwCzPowerState(struct pp_hw_power_state *hw_ps) ++{ ++ if (PhwCz_Magic != hw_ps->magic) ++ return NULL; ++ ++ return (struct cz_power_state *)hw_ps; ++} ++ ++static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr, ++ uint32_t clock, uint32_t msg) ++{ ++ int i = 0; ++ struct phm_clock_voltage_dependency_table *table = ++ hwmgr->dyn_state.vddc_dependency_on_sclk; ++ ++ switch (msg) { ++ case PPSMC_MSG_SetSclkSoftMin: ++ case PPSMC_MSG_SetSclkHardMin: ++ for (i = 0; i < (int)table->count; i++) { ++ if (clock <= table->entries[i].clk) ++ break; ++ } ++ break; ++ ++ case PPSMC_MSG_SetSclkSoftMax: ++ case PPSMC_MSG_SetSclkHardMax: ++ for (i = table->count - 1; i >= 0; i--) { ++ if (clock >= table->entries[i].clk) ++ break; ++ } ++ break; ++ ++ default: ++ break; ++ } ++ return i; ++} ++ ++static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ ++ if (cz_hwmgr->max_sclk_level == 0) { ++ smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel); ++ cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1; ++ } ++ ++ return cz_hwmgr->max_sclk_level; ++} ++ ++static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ uint32_t i; ++ ++ cz_hwmgr->gfx_ramp_step = 256*25/100; ++ ++ cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */ ++ ++ for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) ++ cz_hwmgr->activity_target[i] = CZ_AT_DFLT; ++ ++ cz_hwmgr->mgcg_cgtt_local0 = 0x00000000; ++ cz_hwmgr->mgcg_cgtt_local1 = 0x00000000; ++ ++ cz_hwmgr->clock_slow_down_freq = 25000; ++ ++ cz_hwmgr->skip_clock_slow_down = 1; ++ ++ cz_hwmgr->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */ ++ ++ cz_hwmgr->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */ ++ ++ cz_hwmgr->voting_rights_clients = 0x00C00033; ++ ++ cz_hwmgr->static_screen_threshold = 8; ++ ++ cz_hwmgr->ddi_power_gating_disabled = 0; ++ ++ cz_hwmgr->bapm_enabled = 1; ++ ++ cz_hwmgr->voltage_drop_threshold = 0; ++ ++ cz_hwmgr->gfx_power_gating_threshold = 500; ++ ++ cz_hwmgr->vce_slow_sclk_threshold = 20000; ++ ++ cz_hwmgr->dce_slow_sclk_threshold = 30000; ++ ++ cz_hwmgr->disable_driver_thermal_policy = 1; ++ ++ cz_hwmgr->disable_nb_ps3_in_battery = 0; ++ ++ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, ++ PHM_PlatformCaps_ABM); ++ ++ phm_cap_set(hwmgr->platform_descriptor.platformCaps, ++ PHM_PlatformCaps_NonABMSupportInPPLib); ++ ++ phm_cap_set(hwmgr->platform_descriptor.platformCaps, ++ PHM_PlatformCaps_SclkDeepSleep); ++ ++ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, ++ PHM_PlatformCaps_DynamicM3Arbiter); ++ ++ cz_hwmgr->override_dynamic_mgpg = 1; ++ ++ phm_cap_set(hwmgr->platform_descriptor.platformCaps, ++ PHM_PlatformCaps_DynamicPatchPowerState); ++ ++ cz_hwmgr->thermal_auto_throttling_treshold = 0; ++ ++ cz_hwmgr->tdr_clock = 0; ++ ++ cz_hwmgr->disable_gfx_power_gating_in_uvd = 0; ++ ++ phm_cap_set(hwmgr->platform_descriptor.platformCaps, ++ PHM_PlatformCaps_DynamicUVDState); ++ ++ cz_hwmgr->is_nb_dpm_enabled_by_driver = 1; ++ ++ phm_cap_set(hwmgr->platform_descriptor.platformCaps, ++ PHM_PlatformCaps_DisableVoltageIsland); ++ ++ return 0; ++} ++ ++static uint32_t cz_convert_8Bit_index_to_voltage( ++ struct pp_hwmgr *hwmgr, uint16_t voltage) ++{ ++ return 6200 - (voltage * 25); ++} ++ ++static int cz_construct_max_power_limits_table(struct pp_hwmgr *hwmgr, ++ struct phm_clock_and_voltage_limits *table) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend; ++ struct cz_sys_info *sys_info = &cz_hwmgr->sys_info; ++ struct phm_clock_voltage_dependency_table *dep_table = ++ hwmgr->dyn_state.vddc_dependency_on_sclk; ++ ++ if (dep_table->count > 0) { ++ table->sclk = dep_table->entries[dep_table->count-1].clk; ++ table->vddc = cz_convert_8Bit_index_to_voltage(hwmgr, ++ (uint16_t)dep_table->entries[dep_table->count-1].v); ++ } ++ table->mclk = sys_info->nbp_memory_clock[0]; ++ return 0; ++} ++ ++static int cz_init_dynamic_state_adjustment_rule_settings( ++ struct pp_hwmgr *hwmgr, ++ ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table) ++{ ++ uint32_t table_size = ++ sizeof(struct phm_clock_voltage_dependency_table) + ++ (7 * sizeof(struct phm_clock_voltage_dependency_record)); ++ ++ struct phm_clock_voltage_dependency_table *table_clk_vlt = ++ kzalloc(table_size, GFP_KERNEL); ++ ++ if (NULL == table_clk_vlt) { ++ printk(KERN_ERR "[ powerplay ] Can not allocate memory!\n"); ++ return -ENOMEM; ++ } ++ ++ table_clk_vlt->count = 8; ++ table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0; ++ table_clk_vlt->entries[0].v = 0; ++ table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1; ++ table_clk_vlt->entries[1].v = 1; ++ table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2; ++ table_clk_vlt->entries[2].v = 2; ++ table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3; ++ table_clk_vlt->entries[3].v = 3; ++ table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4; ++ table_clk_vlt->entries[4].v = 4; ++ table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5; ++ table_clk_vlt->entries[5].v = 5; ++ table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6; ++ table_clk_vlt->entries[6].v = 6; ++ table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7; ++ table_clk_vlt->entries[7].v = 7; ++ hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; ++ ++ return 0; ++} ++ ++static int cz_get_system_info_data(struct pp_hwmgr *hwmgr) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend; ++ ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL; ++ uint32_t i; ++ int result = 0; ++ uint8_t frev, crev; ++ uint16_t size; ++ ++ info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *) cgs_atom_get_data_table( ++ hwmgr->device, ++ GetIndexIntoMasterTable(DATA, IntegratedSystemInfo), ++ &size, &frev, &crev); ++ ++ if (crev != 9) { ++ printk(KERN_ERR "[ powerplay ] Unsupported IGP table: %d %d\n", frev, crev); ++ return -EINVAL; ++ } ++ ++ if (info == NULL) { ++ printk(KERN_ERR "[ powerplay ] Could not retrieve the Integrated System Info Table!\n"); ++ return -EINVAL; ++ } ++ ++ cz_hwmgr->sys_info.bootup_uma_clock = ++ le32_to_cpu(info->ulBootUpUMAClock); ++ ++ cz_hwmgr->sys_info.bootup_engine_clock = ++ le32_to_cpu(info->ulBootUpEngineClock); ++ ++ cz_hwmgr->sys_info.dentist_vco_freq = ++ le32_to_cpu(info->ulDentistVCOFreq); ++ ++ cz_hwmgr->sys_info.system_config = ++ le32_to_cpu(info->ulSystemConfig); ++ ++ cz_hwmgr->sys_info.bootup_nb_voltage_index = ++ le16_to_cpu(info->usBootUpNBVoltage); ++ ++ cz_hwmgr->sys_info.htc_hyst_lmt = ++ (info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt; ++ ++ cz_hwmgr->sys_info.htc_tmp_lmt = ++ (info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt; ++ ++ if (cz_hwmgr->sys_info.htc_tmp_lmt <= ++ cz_hwmgr->sys_info.htc_hyst_lmt) { ++ printk(KERN_ERR "[ powerplay ] The htcTmpLmt should be larger than htcHystLmt.\n"); ++ return -EINVAL; ++ } ++ ++ cz_hwmgr->sys_info.nb_dpm_enable = ++ cz_hwmgr->enable_nb_ps_policy && ++ (le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1); ++ ++ for (i = 0; i < CZ_NUM_NBPSTATES; i++) { ++ if (i < CZ_NUM_NBPMEMORYCLOCK) { ++ cz_hwmgr->sys_info.nbp_memory_clock[i] = ++ le32_to_cpu(info->ulNbpStateMemclkFreq[i]); ++ } ++ cz_hwmgr->sys_info.nbp_n_clock[i] = ++ le32_to_cpu(info->ulNbpStateNClkFreq[i]); ++ } ++ ++ for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) { ++ cz_hwmgr->sys_info.display_clock[i] = ++ le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK); ++ } ++ ++ /* Here use 4 levels, make sure not exceed */ ++ for (i = 0; i < CZ_NUM_NBPSTATES; i++) { ++ cz_hwmgr->sys_info.nbp_voltage_index[i] = ++ le16_to_cpu(info->usNBPStateVoltage[i]); ++ } ++ ++ if (!cz_hwmgr->sys_info.nb_dpm_enable) { ++ for (i = 1; i < CZ_NUM_NBPSTATES; i++) { ++ if (i < CZ_NUM_NBPMEMORYCLOCK) { ++ cz_hwmgr->sys_info.nbp_memory_clock[i] = ++ cz_hwmgr->sys_info.nbp_memory_clock[0]; ++ } ++ cz_hwmgr->sys_info.nbp_n_clock[i] = ++ cz_hwmgr->sys_info.nbp_n_clock[0]; ++ cz_hwmgr->sys_info.nbp_voltage_index[i] = ++ cz_hwmgr->sys_info.nbp_voltage_index[0]; ++ } ++ } ++ ++ if (le32_to_cpu(info->ulGPUCapInfo) & ++ SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) { ++ phm_cap_set(hwmgr->platform_descriptor.platformCaps, ++ PHM_PlatformCaps_EnableDFSBypass); ++ } ++ ++ cz_hwmgr->sys_info.uma_channel_number = info->ucUMAChannelNumber; ++ ++ cz_construct_max_power_limits_table (hwmgr, ++ &hwmgr->dyn_state.max_clock_voltage_on_ac); ++ ++ cz_init_dynamic_state_adjustment_rule_settings(hwmgr, ++ &info->sDISPCLK_Voltage[0]); ++ ++ return result; ++} ++ ++static int cz_construct_boot_state(struct pp_hwmgr *hwmgr) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ ++ cz_hwmgr->boot_power_level.engineClock = ++ cz_hwmgr->sys_info.bootup_engine_clock; ++ ++ cz_hwmgr->boot_power_level.vddcIndex = ++ (uint8_t)cz_hwmgr->sys_info.bootup_nb_voltage_index; ++ ++ cz_hwmgr->boot_power_level.dsDividerIndex = 0; ++ ++ cz_hwmgr->boot_power_level.ssDividerIndex = 0; ++ ++ cz_hwmgr->boot_power_level.allowGnbSlow = 1; ++ ++ cz_hwmgr->boot_power_level.forceNBPstate = 0; ++ ++ cz_hwmgr->boot_power_level.hysteresis_up = 0; ++ ++ cz_hwmgr->boot_power_level.numSIMDToPowerDown = 0; ++ ++ cz_hwmgr->boot_power_level.display_wm = 0; ++ ++ cz_hwmgr->boot_power_level.vce_wm = 0; ++ ++ return 0; ++} ++ ++static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input, ++ void *output, void *storage, int result) ++{ ++ return 0; ++} ++ ++static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input, ++ void *output, void *storage, int result) ++{ ++ return 0; ++} ++ ++static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input, ++ void *output, void *storage, int result) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ struct phm_clock_voltage_dependency_table *table = ++ hwmgr->dyn_state.vddc_dependency_on_sclk; ++ unsigned long clock = 0, level; ++ ++ if (NULL == table && table->count <= 0) ++ return -EINVAL; ++ ++ cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk; ++ cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk; ++ ++ level = cz_get_max_sclk_level(hwmgr) - 1; ++ ++ if (level < table->count) ++ clock = table->entries[level].clk; ++ else ++ clock = table->entries[table->count - 1].clk; ++ ++ cz_hwmgr->sclk_dpm.soft_max_clk = clock; ++ cz_hwmgr->sclk_dpm.hard_max_clk = clock; ++ ++ return 0; ++} ++ ++static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input, ++ void *output, void *storage, int result) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ struct phm_uvd_clock_voltage_dependency_table *table = ++ hwmgr->dyn_state.uvd_clocl_voltage_dependency_table; ++ unsigned long clock = 0, level; ++ ++ if (NULL == table && table->count <= 0) ++ return -EINVAL; ++ ++ cz_hwmgr->uvd_dpm.soft_min_clk = 0; ++ cz_hwmgr->uvd_dpm.hard_min_clk = 0; ++ ++ smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel); ++ level = smum_get_argument(hwmgr->smumgr); ++ ++ if (level < table->count) ++ clock = table->entries[level].vclk; ++ else ++ clock = table->entries[table->count - 1].vclk; ++ ++ cz_hwmgr->uvd_dpm.soft_max_clk = clock; ++ cz_hwmgr->uvd_dpm.hard_max_clk = clock; ++ ++ return 0; ++} ++ ++static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input, ++ void *output, void *storage, int result) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ struct phm_vce_clock_voltage_dependency_table *table = ++ hwmgr->dyn_state.vce_clocl_voltage_dependency_table; ++ unsigned long clock = 0, level; ++ ++ if (NULL == table && table->count <= 0) ++ return -EINVAL; ++ ++ cz_hwmgr->vce_dpm.soft_min_clk = 0; ++ cz_hwmgr->vce_dpm.hard_min_clk = 0; ++ ++ smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel); ++ level = smum_get_argument(hwmgr->smumgr); ++ ++ if (level < table->count) ++ clock = table->entries[level].ecclk; ++ else ++ clock = table->entries[table->count - 1].ecclk; ++ ++ cz_hwmgr->vce_dpm.soft_max_clk = clock; ++ cz_hwmgr->vce_dpm.hard_max_clk = clock; ++ ++ return 0; ++} ++ ++static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input, ++ void *output, void *storage, int result) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ struct phm_acp_clock_voltage_dependency_table *table = ++ hwmgr->dyn_state.acp_clock_voltage_dependency_table; ++ unsigned long clock = 0, level; ++ ++ if (NULL == table && table->count <= 0) ++ return -EINVAL; ++ ++ cz_hwmgr->acp_dpm.soft_min_clk = 0; ++ cz_hwmgr->acp_dpm.hard_min_clk = 0; ++ ++ smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel); ++ level = smum_get_argument(hwmgr->smumgr); ++ ++ if (level < table->count) ++ clock = table->entries[level].acpclk; ++ else ++ clock = table->entries[table->count - 1].acpclk; ++ ++ cz_hwmgr->acp_dpm.soft_max_clk = clock; ++ cz_hwmgr->acp_dpm.hard_max_clk = clock; ++ return 0; ++} ++ ++static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input, ++ void *output, void *storage, int result) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ ++ cz_hwmgr->uvd_power_gated = false; ++ cz_hwmgr->vce_power_gated = false; ++ cz_hwmgr->samu_power_gated = false; ++ cz_hwmgr->acp_power_gated = false; ++ cz_hwmgr->pgacpinit = true; ++ ++ return 0; ++} ++ ++static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input, ++ void *output, void *storage, int result) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ ++ cz_hwmgr->low_sclk_interrupt_threshold = 0; ++ ++ return 0; ++} ++ ++static struct phm_master_table_item cz_setup_asic_list[] = { ++ {NULL, cz_tf_reset_active_process_mask}, ++ {NULL, cz_tf_upload_pptable_to_smu}, ++ {NULL, cz_tf_init_sclk_limit}, ++ {NULL, cz_tf_init_uvd_limit}, ++ {NULL, cz_tf_init_vce_limit}, ++ {NULL, cz_tf_init_acp_limit}, ++ {NULL, cz_tf_init_power_gate_state}, ++ {NULL, cz_tf_init_sclk_threshold}, ++ {NULL, NULL} ++}; ++ ++static struct phm_master_table_header cz_setup_asic_master = { ++ 0, ++ PHM_MasterTableFlag_None, ++ cz_setup_asic_list ++}; ++ ++static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input, ++ void *output, void *storage, int result) ++{ ++ PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0, ++ PPCZ_VOTINGRIGHTSCLIENTS_DFLT0); ++ return 0; ++} ++ ++static int cz_tf_start_dpm(struct pp_hwmgr *hwmgr, void *input, void *output, ++ void *storage, int result) ++{ ++ int res = 0xff; ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ unsigned long dpm_features = 0; ++ ++ cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled; ++ dpm_features |= SCLK_DPM_MASK; ++ ++ res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, ++ PPSMC_MSG_EnableAllSmuFeatures, ++ dpm_features); ++ ++ return res; ++} ++ ++static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input, ++ void *output, void *storage, int result) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ ++ cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock; ++ cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock; ++ ++ smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, ++ PPSMC_MSG_SetSclkSoftMin, ++ cz_get_sclk_level(hwmgr, ++ cz_hwmgr->sclk_dpm.soft_min_clk, ++ PPSMC_MSG_SetSclkSoftMin)); ++ ++ smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, ++ PPSMC_MSG_SetSclkSoftMax, ++ cz_get_sclk_level(hwmgr, ++ cz_hwmgr->sclk_dpm.soft_max_clk, ++ PPSMC_MSG_SetSclkSoftMax)); ++ ++ return 0; ++} ++ ++int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input, ++ void *output, void *storage, int result) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ ++ cz_hwmgr->acp_boot_level = 0xff; ++ return 0; ++} ++ ++static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr, ++ unsigned long check_feature) ++{ ++ int result; ++ unsigned long features; ++ ++ result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0); ++ if (result == 0) { ++ features = smum_get_argument(hwmgr->smumgr); ++ if (features & check_feature) ++ return true; ++ } ++ ++ return result; ++} ++ ++static int cz_tf_check_for_dpm_disabled(struct pp_hwmgr *hwmgr, void *input, ++ void *output, void *storage, int result) ++{ ++ if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn)) ++ return PP_Result_TableImmediateExit; ++ return 0; ++} ++ ++static int cz_tf_enable_didt(struct pp_hwmgr *hwmgr, void *input, ++ void *output, void *storage, int result) ++{ ++ /* TO DO */ ++ return 0; ++} ++ ++static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr, ++ void *input, void *output, ++ void *storage, int result) ++{ ++ if (!cz_dpm_check_smu_features(hwmgr, ++ SMU_EnabledFeatureScoreboard_SclkDpmOn)) ++ return PP_Result_TableImmediateExit; ++ return 0; ++} ++ ++static struct phm_master_table_item cz_disable_dpm_list[] = { ++ { NULL, cz_tf_check_for_dpm_enabled}, ++ {NULL, NULL}, ++}; ++ ++ ++static struct phm_master_table_header cz_disable_dpm_master = { ++ 0, ++ PHM_MasterTableFlag_None, ++ cz_disable_dpm_list ++}; ++ ++static struct phm_master_table_item cz_enable_dpm_list[] = { ++ { NULL, cz_tf_check_for_dpm_disabled }, ++ { NULL, cz_tf_program_voting_clients }, ++ { NULL, cz_tf_start_dpm}, ++ { NULL, cz_tf_program_bootup_state}, ++ { NULL, cz_tf_enable_didt }, ++ { NULL, cz_tf_reset_acp_boot_level }, ++ {NULL, NULL}, ++}; ++ ++static struct phm_master_table_header cz_enable_dpm_master = { ++ 0, ++ PHM_MasterTableFlag_None, ++ cz_enable_dpm_list ++}; ++ ++static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr) ++{ ++ int result = 0; ++ ++ result = cz_initialize_dpm_defaults(hwmgr); ++ if (result != 0) { ++ printk(KERN_ERR "[ powerplay ] cz_initialize_dpm_defaults failed\n"); ++ return result; ++ } ++ ++ result = cz_get_system_info_data(hwmgr); ++ if (result != 0) { ++ printk(KERN_ERR "[ powerplay ] cz_get_system_info_data failed\n"); ++ return result; ++ } ++ ++ cz_construct_boot_state(hwmgr); ++ ++ result = phm_construct_table(hwmgr, &cz_setup_asic_master, ++ &(hwmgr->setup_asic)); ++ if (result != 0) { ++ printk(KERN_ERR "[ powerplay ] Fail to construct setup ASIC\n"); ++ return result; ++ } ++ ++ result = phm_construct_table(hwmgr, &cz_disable_dpm_master, ++ &(hwmgr->disable_dynamic_state_management)); ++ ++ result = phm_construct_table(hwmgr, &cz_enable_dpm_master, ++ &(hwmgr->enable_dynamic_state_management)); ++ ++ return result; ++} ++ ++static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) ++{ ++ if (hwmgr != NULL || hwmgr->backend != NULL) { ++ kfree(hwmgr->backend); ++ kfree(hwmgr); ++ } ++ return 0; ++} ++ ++int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ ++ if (cz_hwmgr->sclk_dpm.soft_min_clk != ++ cz_hwmgr->sclk_dpm.soft_max_clk) ++ smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, ++ PPSMC_MSG_SetSclkSoftMin, ++ cz_get_sclk_level(hwmgr, ++ cz_hwmgr->sclk_dpm.soft_max_clk, ++ PPSMC_MSG_SetSclkSoftMin)); ++ return 0; ++} ++ ++int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ struct phm_clock_voltage_dependency_table *table = ++ hwmgr->dyn_state.vddc_dependency_on_sclk; ++ unsigned long clock = 0, level; ++ ++ if (NULL == table && table->count <= 0) ++ return -EINVAL; ++ ++ cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk; ++ cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk; ++ ++ level = cz_get_max_sclk_level(hwmgr) - 1; ++ ++ if (level < table->count) ++ clock = table->entries[level].clk; ++ else ++ clock = table->entries[table->count - 1].clk; ++ ++ cz_hwmgr->sclk_dpm.soft_max_clk = clock; ++ cz_hwmgr->sclk_dpm.hard_max_clk = clock; ++ ++ smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, ++ PPSMC_MSG_SetSclkSoftMin, ++ cz_get_sclk_level(hwmgr, ++ cz_hwmgr->sclk_dpm.soft_min_clk, ++ PPSMC_MSG_SetSclkSoftMin)); ++ ++ smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, ++ PPSMC_MSG_SetSclkSoftMax, ++ cz_get_sclk_level(hwmgr, ++ cz_hwmgr->sclk_dpm.soft_max_clk, ++ PPSMC_MSG_SetSclkSoftMax)); ++ ++ return 0; ++} ++ ++int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ ++ if (cz_hwmgr->sclk_dpm.soft_min_clk != ++ cz_hwmgr->sclk_dpm.soft_max_clk) { ++ cz_hwmgr->sclk_dpm.soft_max_clk = ++ cz_hwmgr->sclk_dpm.soft_min_clk; ++ ++ smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, ++ PPSMC_MSG_SetSclkSoftMax, ++ cz_get_sclk_level(hwmgr, ++ cz_hwmgr->sclk_dpm.soft_max_clk, ++ PPSMC_MSG_SetSclkSoftMax)); ++ } ++ ++ return 0; ++} ++ ++static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, ++ enum amd_dpm_forced_level level) ++{ ++ int ret = 0; ++ ++ switch (level) { ++ case AMD_DPM_FORCED_LEVEL_HIGH: ++ ret = cz_phm_force_dpm_highest(hwmgr); ++ if (ret) ++ return ret; ++ break; ++ case AMD_DPM_FORCED_LEVEL_LOW: ++ ret = cz_phm_force_dpm_lowest(hwmgr); ++ if (ret) ++ return ret; ++ break; ++ case AMD_DPM_FORCED_LEVEL_AUTO: ++ ret = cz_phm_unforce_dpm_levels(hwmgr); ++ if (ret) ++ return ret; ++ break; ++ default: ++ break; ++ } ++ ++ hwmgr->dpm_level = level; ++ ++ return ret; ++} ++ ++static int cz_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, ++ struct pp_hw_power_state *hw_ps) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps); ++ ++ cz_ps->level = 1; ++ cz_ps->nbps_flags = 0; ++ cz_ps->bapm_flags = 0; ++ cz_ps->levels[0] = cz_hwmgr->boot_power_level; ++ ++ return 0; ++} ++ ++static int cz_dpm_get_pp_table_entry_callback( ++ struct pp_hwmgr *hwmgr, ++ struct pp_hw_power_state *hw_ps, ++ unsigned int index, ++ const void *clock_info) ++{ ++ struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps); ++ ++ const ATOM_PPLIB_CZ_CLOCK_INFO *cz_clock_info = clock_info; ++ ++ struct phm_clock_voltage_dependency_table *table = ++ hwmgr->dyn_state.vddc_dependency_on_sclk; ++ uint8_t clock_info_index = cz_clock_info->index; ++ ++ if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1)) ++ clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1); ++ ++ cz_ps->levels[index].engineClock = table->entries[clock_info_index].clk; ++ cz_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v; ++ ++ cz_ps->level = index + 1; ++ ++ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { ++ cz_ps->levels[index].dsDividerIndex = 5; ++ cz_ps->levels[index].ssDividerIndex = 5; ++ } ++ ++ return 0; ++} ++ ++static int cz_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr) ++{ ++ int result; ++ unsigned long ret = 0; ++ ++ result = pp_tables_get_num_of_entries(hwmgr, &ret); ++ ++ return result ? 0 : ret; ++} ++ ++static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr, ++ unsigned long entry, struct pp_power_state *ps) ++{ ++ int result; ++ struct cz_power_state *cz_ps; ++ ++ ps->hardware.magic = PhwCz_Magic; ++ ++ cz_ps = cast_PhwCzPowerState(&(ps->hardware)); ++ ++ result = pp_tables_get_entry(hwmgr, entry, ps, ++ cz_dpm_get_pp_table_entry_callback); ++ ++ cz_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; ++ cz_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; ++ ++ return result; ++} ++ ++int cz_get_power_state_size(struct pp_hwmgr *hwmgr) ++{ ++ return sizeof(struct cz_power_state); ++} ++ ++static const struct pp_hwmgr_func cz_hwmgr_funcs = { ++ .backend_init = cz_hwmgr_backend_init, ++ .backend_fini = cz_hwmgr_backend_fini, ++ .asic_setup = NULL, ++ .force_dpm_level = cz_dpm_force_dpm_level, ++ .get_power_state_size = cz_get_power_state_size, ++ .patch_boot_state = cz_dpm_patch_boot_state, ++ .get_pp_table_entry = cz_dpm_get_pp_table_entry, ++ .get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries, ++}; ++ ++int cz_hwmgr_init(struct pp_hwmgr *hwmgr) ++{ ++ struct cz_hwmgr *cz_hwmgr; ++ int ret = 0; ++ ++ cz_hwmgr = kzalloc(sizeof(struct cz_hwmgr), GFP_KERNEL); ++ if (cz_hwmgr == NULL) ++ return -ENOMEM; ++ ++ hwmgr->backend = cz_hwmgr; ++ hwmgr->hwmgr_func = &cz_hwmgr_funcs; ++ hwmgr->pptable_func = &pptable_funcs; ++ return ret; ++} +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h +new file mode 100644 +index 0000000..05849fd +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h +@@ -0,0 +1,309 @@ ++/* ++ * Copyright 2015 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++ ++#ifndef _CZ_HWMGR_H_ ++#define _CZ_HWMGR_H_ ++ ++#include "cgs_common.h" ++ ++#define CZ_NUM_NBPSTATES 4 ++#define CZ_NUM_NBPMEMORYCLOCK 2 ++#define MAX_DISPLAY_CLOCK_LEVEL 8 ++#define CZ_AT_DFLT 30 ++#define CZ_MAX_HARDWARE_POWERLEVELS 8 ++#define PPCZ_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102 ++ ++/* Carrizo device IDs */ ++#define DEVICE_ID_CZ_9870 0x9870 ++#define DEVICE_ID_CZ_9874 0x9874 ++#define DEVICE_ID_CZ_9875 0x9875 ++#define DEVICE_ID_CZ_9876 0x9876 ++#define DEVICE_ID_CZ_9877 0x9877 ++ ++#define PHMCZ_WRITE_SMC_REGISTER(device, reg, value) \ ++ cgs_write_ind_register(device, CGS_IND_REG__SMC, ix##reg, value) ++ ++struct cz_dpm_entry { ++ uint32_t soft_min_clk; ++ uint32_t hard_min_clk; ++ uint32_t soft_max_clk; ++ uint32_t hard_max_clk; ++}; ++ ++struct cz_sys_info { ++ uint32_t bootup_uma_clock; ++ uint32_t bootup_engine_clock; ++ uint32_t dentist_vco_freq; ++ uint32_t nb_dpm_enable; ++ uint32_t nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK]; ++ uint32_t nbp_n_clock[CZ_NUM_NBPSTATES]; ++ uint16_t nbp_voltage_index[CZ_NUM_NBPSTATES]; ++ uint32_t display_clock[MAX_DISPLAY_CLOCK_LEVEL]; ++ uint16_t bootup_nb_voltage_index; ++ uint8_t htc_tmp_lmt; ++ uint8_t htc_hyst_lmt; ++ uint32_t system_config; ++ uint32_t uma_channel_number; ++}; ++ ++#define MAX_DISPLAYPHY_IDS 0x8 ++#define DISPLAYPHY_LANEMASK 0xF ++#define UNKNOWN_TRANSMITTER_PHY_ID (-1) ++ ++#define DISPLAYPHY_PHYID_SHIFT 24 ++#define DISPLAYPHY_LANESELECT_SHIFT 16 ++ ++#define DISPLAYPHY_RX_SELECT 0x1 ++#define DISPLAYPHY_TX_SELECT 0x2 ++#define DISPLAYPHY_CORE_SELECT 0x4 ++ ++#define DDI_POWERGATING_ARG(phyID, lanemask, rx, tx, core) \ ++ (((uint32_t)(phyID))<<DISPLAYPHY_PHYID_SHIFT | \ ++ ((uint32_t)(lanemask))<<DISPLAYPHY_LANESELECT_SHIFT | \ ++ ((rx) ? DISPLAYPHY_RX_SELECT : 0) | \ ++ ((tx) ? DISPLAYPHY_TX_SELECT : 0) | \ ++ ((core) ? DISPLAYPHY_CORE_SELECT : 0)) ++ ++struct cz_display_phy_info_entry { ++ uint8_t phy_present; ++ uint8_t active_lane_mapping; ++ uint8_t display_config_type; ++ uint8_t active_number_of_lanes; ++}; ++ ++#define CZ_MAX_DISPLAYPHY_IDS 10 ++ ++struct cz_display_phy_info { ++ bool display_phy_access_initialized; ++ struct cz_display_phy_info_entry entries[CZ_MAX_DISPLAYPHY_IDS]; ++}; ++ ++struct cz_power_level { ++ uint32_t engineClock; ++ uint8_t vddcIndex; ++ uint8_t dsDividerIndex; ++ uint8_t ssDividerIndex; ++ uint8_t allowGnbSlow; ++ uint8_t forceNBPstate; ++ uint8_t display_wm; ++ uint8_t vce_wm; ++ uint8_t numSIMDToPowerDown; ++ uint8_t hysteresis_up; ++ uint8_t rsv[3]; ++}; ++ ++struct cz_uvd_clocks { ++ uint32_t vclk; ++ uint32_t dclk; ++ uint32_t vclk_low_divider; ++ uint32_t vclk_high_divider; ++ uint32_t dclk_low_divider; ++ uint32_t dclk_high_divider; ++}; ++ ++enum cz_pstate_previous_action { ++ DO_NOTHING = 1, ++ FORCE_HIGH, ++ CANCEL_FORCE_HIGH ++}; ++ ++struct pp_disable_nb_ps_flags { ++ union { ++ struct { ++ uint32_t entry : 1; ++ uint32_t display : 1; ++ uint32_t driver: 1; ++ uint32_t vce : 1; ++ uint32_t uvd : 1; ++ uint32_t acp : 1; ++ uint32_t reserved: 26; ++ } bits; ++ uint32_t u32All; ++ }; ++}; ++ ++struct cz_power_state { ++ unsigned int magic; ++ uint32_t level; ++ struct cz_uvd_clocks uvd_clocks; ++ uint32_t evclk; ++ uint32_t ecclk; ++ uint32_t samclk; ++ uint32_t acpclk; ++ bool need_dfs_bypass; ++ uint32_t nbps_flags; ++ uint32_t bapm_flags; ++ uint8_t dpm_0_pg_nb_ps_low; ++ uint8_t dpm_0_pg_nb_ps_high; ++ uint8_t dpm_x_nb_ps_low; ++ uint8_t dpm_x_nb_ps_high; ++ enum cz_pstate_previous_action action; ++ struct cz_power_level levels[CZ_MAX_HARDWARE_POWERLEVELS]; ++ struct pp_disable_nb_ps_flags disable_nb_ps_flag; ++}; ++ ++#define DPMFlags_SCLK_Enabled 0x00000001 ++#define DPMFlags_UVD_Enabled 0x00000002 ++#define DPMFlags_VCE_Enabled 0x00000004 ++#define DPMFlags_ACP_Enabled 0x00000008 ++#define DPMFlags_ForceHighestValid 0x40000000 ++#define DPMFlags_Debug 0x80000000 ++ ++#define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001 /* bit 0 */ ++#define SMU_EnabledFeatureScoreboard_SclkDpmOn 0x00200000 ++#define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x00800000 /* bit 23 */ ++#define SMU_EnabledFeatureScoreboard_VceDpmOn 0x01000000 /* bit 24 */ ++ ++struct cz_hwmgr { ++ uint32_t activity_target[CZ_MAX_HARDWARE_POWERLEVELS]; ++ uint32_t dpm_interval; ++ ++ uint32_t voltage_drop_threshold; ++ ++ uint32_t voting_rights_clients; ++ ++ uint32_t disable_driver_thermal_policy; ++ ++ uint32_t static_screen_threshold; ++ ++ uint32_t gfx_power_gating_threshold; ++ ++ uint32_t activity_hysteresis; ++ uint32_t bootup_sclk_divider; ++ uint32_t gfx_ramp_step; ++ uint32_t gfx_ramp_delay; /* in micro-seconds */ ++ ++ uint32_t thermal_auto_throttling_treshold; ++ ++ struct cz_sys_info sys_info; ++ ++ struct cz_power_level boot_power_level; ++ uint32_t mgcg_cgtt_local0; ++ uint32_t mgcg_cgtt_local1; ++ ++ uint32_t tdr_clock; /* in 10khz unit */ ++ ++ uint32_t ddi_power_gating_disabled; ++ uint32_t disable_gfx_power_gating_in_uvd; ++ uint32_t disable_nb_ps3_in_battery; ++ ++ uint32_t lock_nb_ps_in_uvd_play_back; ++ ++ struct cz_display_phy_info display_phy_info; ++ uint32_t vce_slow_sclk_threshold; /* default 200mhz */ ++ uint32_t dce_slow_sclk_threshold; /* default 300mhz */ ++ uint32_t min_sclk_did; /* minimum sclk divider */ ++ ++ bool disp_clk_bypass; ++ bool disp_clk_bypass_pending; ++ uint32_t bapm_enabled; ++ uint32_t clock_slow_down_freq; ++ uint32_t skip_clock_slow_down; ++ uint32_t enable_nb_ps_policy; ++ uint32_t voltage_drop_in_dce_power_gating; ++ uint32_t uvd_dpm_interval; ++ uint32_t override_dynamic_mgpg; ++ uint32_t lclk_deep_enabled; ++ ++ uint32_t uvd_performance; ++ ++ bool video_start; ++ bool battery_state; ++ uint32_t lowest_valid; ++ uint32_t highest_valid; ++ uint32_t high_voltage_threshold; ++ uint32_t is_nb_dpm_enabled; ++ uint32_t is_nb_dpm_enabled_by_driver; ++ uint32_t is_voltage_island_enabled; ++ ++ bool pgacpinit; ++ ++ uint8_t disp_config; ++ ++ /* PowerTune */ ++ uint32_t power_containment_features; ++ bool cac_enabled; ++ bool disable_uvd_power_tune_feature; ++ bool enable_ba_pm_feature; ++ bool enable_tdc_limit_feature; ++ ++ uint32_t sram_end; ++ uint32_t dpm_table_start; ++ uint32_t soft_regs_start; ++ ++ uint8_t uvd_level_count; ++ uint8_t vce_level_count; ++ ++ uint8_t acp_level_count; ++ uint8_t samu_level_count; ++ uint32_t fps_high_threshold; ++ uint32_t fps_low_threshold; ++ ++ uint32_t dpm_flags; ++ struct cz_dpm_entry sclk_dpm; ++ struct cz_dpm_entry uvd_dpm; ++ struct cz_dpm_entry vce_dpm; ++ struct cz_dpm_entry acp_dpm; ++ ++ uint8_t uvd_boot_level; ++ uint8_t vce_boot_level; ++ uint8_t acp_boot_level; ++ uint8_t samu_boot_level; ++ uint8_t uvd_interval; ++ uint8_t vce_interval; ++ uint8_t acp_interval; ++ uint8_t samu_interval; ++ ++ uint8_t graphics_interval; ++ uint8_t graphics_therm_throttle_enable; ++ uint8_t graphics_voltage_change_enable; ++ ++ uint8_t graphics_clk_slow_enable; ++ uint8_t graphics_clk_slow_divider; ++ ++ uint32_t display_cac; ++ uint32_t low_sclk_interrupt_threshold; ++ ++ uint32_t dram_log_addr_h; ++ uint32_t dram_log_addr_l; ++ uint32_t dram_log_phy_addr_h; ++ uint32_t dram_log_phy_addr_l; ++ uint32_t dram_log_buff_size; ++ ++ bool uvd_power_gated; ++ bool vce_power_gated; ++ bool samu_power_gated; ++ bool acp_power_gated; ++ bool acp_power_up_no_dsp; ++ uint32_t active_process_mask; ++ ++ uint32_t max_sclk_level; ++ uint32_t num_of_clk_entries; ++ struct cz_power_state *cz_ps; ++}; ++ ++struct pp_hwmgr; ++ ++int cz_hwmgr_init(struct pp_hwmgr *hwmgr); ++ ++#endif /* _CZ_HWMGR_H_ */ +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +index f6b1153..e26df90 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +@@ -27,8 +27,7 @@ + #include "cgs_common.h" + #include "power_state.h" + #include "hwmgr.h" +- +- ++#include "cz_hwmgr.h" + + int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle) + { +@@ -51,6 +50,9 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle) + hwmgr->power_source = PP_PowerSource_AC; + + switch (hwmgr->chip_family) { ++ case AMD_FAMILY_CZ: ++ cz_hwmgr_init(hwmgr); ++ break; + default: + return -EINVAL; + } +-- +2.7.4 + |