diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/9058-amd-xgbe-AIC2-rx-adaption-software-tuning-enablement.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/9058-amd-xgbe-AIC2-rx-adaption-software-tuning-enablement.patch | 218 |
1 files changed, 218 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/9058-amd-xgbe-AIC2-rx-adaption-software-tuning-enablement.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/9058-amd-xgbe-AIC2-rx-adaption-software-tuning-enablement.patch new file mode 100644 index 00000000..d56d3f14 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/9058-amd-xgbe-AIC2-rx-adaption-software-tuning-enablement.patch @@ -0,0 +1,218 @@ +From 2f8aa57b60992e0ea49f2d597f844c01623e7782 Mon Sep 17 00:00:00 2001 +From: rgaridap <Ramesh.Garidapuri@amd.com> +Date: Tue, 23 Aug 2022 16:17:29 +0530 +Subject: [PATCH] amd-xgbe:AIC2 rx-adaption software tuning enablement + +Change-Id: Ib7b6b8db42767a49f848428ac5e03790983e3d3a +--- + drivers/net/ethernet/amd/xgbe/xgbe-mdio.c | 4 -- + drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c | 67 +++++++++++++++++---- + drivers/net/ethernet/amd/xgbe/xgbe.h | 1 + + drivers/net/phy/aquantia_main.c | 5 +- + 4 files changed, 61 insertions(+), 16 deletions(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c +index d0b2179e9078..c3fdcbb1df98 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c +@@ -1309,10 +1309,6 @@ static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata) + if (pdata->an_mode == XGBE_AN_MODE_MDIO) { + if(pdata->phy.link) + pdata->an_result = XGBE_AN_COMPLETE; +- else { +- netif_dbg(pdata, link, pdata->netdev, "xgbe_phy_aneg_done : ******* Forcing next mode ******* \n"); +- pdata->an_result = XGBE_AN_NO_LINK; +- } + } + return (pdata->an_result == XGBE_AN_COMPLETE); + } +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c +index 278e0509cd19..b067f8216710 100644 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c +@@ -1868,7 +1868,7 @@ static enum xgbe_mode xgbe_phy_mdio_an_outcome(struct xgbe_prv_data *pdata) + mode = XGBE_MODE_KX_2500; + break; + default: +- mode = XGBE_MODE_KR; ++ mode = XGBE_MODE_UNKNOWN; + break; + } + } +@@ -1970,6 +1970,7 @@ static int xgbe_phy_an_config(struct xgbe_prv_data *pdata) + struct ethtool_link_ksettings *lks = &pdata->phy.lks; + struct xgbe_phy_data *phy_data = pdata->phy_data; + int ret; ++ unsigned long link_timeout; + + ret = xgbe_phy_find_phy_device(pdata); + if (ret) +@@ -1986,9 +1987,14 @@ static int xgbe_phy_an_config(struct xgbe_prv_data *pdata) + phy_data->phydev->speed = pdata->phy.speed; + phy_data->phydev->duplex = pdata->phy.duplex; + } ++ netif_dbg(pdata, link, pdata->netdev, " phy_start_aneg \n"); + +- ret = phy_start_aneg(phy_data->phydev); +- ++ link_timeout = pdata->phy_link_check + (XGBE_LINK_TIMEOUT*2 * HZ); ++ if (time_after(jiffies, link_timeout)) { ++ ret = phy_start_aneg(phy_data->phydev); ++ pdata->phy_link_check = jiffies; ++ } ++ + return ret; + } + +@@ -2174,7 +2180,7 @@ static void xgbe_phy_rx_adaptation(struct xgbe_prv_data *pdata) + reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_EQ_CTRL4, 0xffffffff); + netif_dbg(pdata, link, pdata->netdev, "%s MDIO_PMA_RX_EQ_CTRL4 current data 0x%x\n", + __func__, reg); +- ++ + /* step 2: force PCS to send RX_ADAPT Req to PHY */ + XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_EQ_CTRL4, + XGBE_PMA_RX_AD_REQ_MASK, XGBE_PMA_RX_AD_REQ_ENABLE); +@@ -2202,7 +2208,7 @@ static void xgbe_phy_rx_adaptation(struct xgbe_prv_data *pdata) + reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); + if (reg & MDIO_STAT1_LSTATUS) { + /* If the block lock is found, declare the link up */ +- netif_dbg(pdata, link, pdata->netdev, "%s block_lock done\n", __func__); ++ netif_dbg(pdata, link, pdata->netdev, "%s block_lock done and link is up\n", __func__); + pdata->rx_adapt_done = 1; + pdata->mode_set = 0; + return; +@@ -2216,7 +2222,10 @@ static void xgbe_phy_rx_adaptation(struct xgbe_prv_data *pdata) + pdata->rx_adapt_retries = 0; + return; + } +- _xgbe_mode_set(pdata, phy_data->cur_mode); ++ ++ if ((phy_data->cur_mode == XGBE_MODE_KR) ||( phy_data->cur_mode == XGBE_MODE_SFI)) ++ pdata->hw_if.set_speed(pdata, SPEED_10000); ++ _xgbe_mode_set(pdata, phy_data->cur_mode); + } + } else { + netif_dbg(pdata, link, pdata->netdev, "%s either RX_VALID or LF_SIGDET is not set, issuing rrc\n",__func__); +@@ -2310,6 +2319,12 @@ static bool enable_rx_adap(struct xgbe_prv_data *pdata, enum xgbe_mode mode) + { + struct xgbe_phy_data *phy_data = pdata->phy_data; + ++ if ((phy_data->mdio_an_mode) && (mode == XGBE_MODE_KR)) { ++ pdata->en_rx_adap = 1; ++ netif_dbg(pdata, link, pdata->netdev, " pdata->en_rx_adap %d\n", pdata->en_rx_adap); ++ return true; ++ } ++ + if ((pdata->vdata->is_yc) && + (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) { + if ((phy_data->redrv) && +@@ -2415,7 +2430,6 @@ static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata) + struct xgbe_phy_data *phy_data = pdata->phy_data; + + xgbe_phy_set_redrv_mode(pdata); +- + /* 10G/KR */ + if (enable_rx_adap(pdata, XGBE_MODE_KR)) { + xgbe_phy_perform_ratechange(pdata, 4, 1); +@@ -2922,6 +2936,7 @@ static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) + struct xgbe_phy_data *phy_data = pdata->phy_data; + unsigned int reg; + int ret; ++ enum xgbe_mode mode = XGBE_MODE_UNKNOWN; + + *an_restart = 0; + +@@ -2948,13 +2963,41 @@ static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) + return 0; + + if ((pdata->phy.autoneg == AUTONEG_ENABLE) && +- !phy_aneg_done(phy_data->phydev)) ++ !phy_aneg_done(phy_data->phydev)) { ++ if (enable_rx_adap(pdata, XGBE_MODE_KR)) ++ pdata->rx_adapt_done = 0; ++ pdata->an_result = XGBE_AN_READY; ++ if (!test_bit(XGBE_LINK_INIT, &pdata->dev_state)) { ++ netif_carrier_off(pdata->netdev); ++ *an_restart = 1; ++ } /*should not restart AN within 5 seconds for AQR, AQR will restart after 15s ++ or keep 10 sec between AN restart*/ + return 0; ++ } else { ++ pdata->an_result = XGBE_AN_COMPLETE; ++ } + +- if (!phy_data->phydev->link) ++ ++ if (!phy_data->phydev->link) { ++ if (enable_rx_adap(pdata, XGBE_MODE_KR)) ++ pdata->rx_adapt_done = 0; + return 0; +- if (pdata->an_mode == XGBE_AN_MODE_MDIO) +- return 1; ++ } ++ if (pdata->an_mode == XGBE_AN_MODE_MDIO) { ++ mode = xgbe_phy_mdio_an_outcome(pdata); ++ /* Set MAC to 10G speed and set mode to enable Rx adaptation*/ ++ if(mode == XGBE_MODE_KR) { ++ enable_rx_adap(pdata, XGBE_MODE_KR); ++ if(pdata->rx_adapt_done == 0) { ++ pdata->hw_if.set_speed(pdata, SPEED_10000); ++ xgbe_phy_set_mode(pdata, mode); ++ if(pdata->rx_adapt_done == 0) ++ xgbe_phy_rx_adaptation(pdata); ++ } ++ } ++ if(mode == XGBE_MODE_UNKNOWN) ++ return 0; ++ } + } + + /* Link status is latched low, so read once to clear +@@ -2976,6 +3019,8 @@ static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) + xgbe_phy_set_mode(pdata, phy_data->cur_mode); + } + ++ reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); ++ reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); + /* check again for the link and adaptation status */ + if ((reg & MDIO_STAT1_LSTATUS) && (pdata->rx_adapt_done)) + return 1; +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h +index 895712fcbbd3..2c244aa15c27 100644 +--- a/drivers/net/ethernet/amd/xgbe/xgbe.h ++++ b/drivers/net/ethernet/amd/xgbe/xgbe.h +@@ -1241,6 +1241,7 @@ struct xgbe_prv_data { + struct xgbe_phy phy; + int mdio_mmd; + unsigned long link_check; ++ unsigned long phy_link_check; + struct completion mdio_complete; + + unsigned int kr_redrv; +diff --git a/drivers/net/phy/aquantia_main.c b/drivers/net/phy/aquantia_main.c +index 402b93829c86..28329c281e75 100755 +--- a/drivers/net/phy/aquantia_main.c ++++ b/drivers/net/phy/aquantia_main.c +@@ -299,6 +299,7 @@ static int aqr113_set_mode(struct phy_device *phydev) + + static int aqr113_config_aneg(struct phy_device *phydev) + { ++ phydev_dbg(phydev, " AQR AN start "); + aqr113_set_mode(phydev); + return aqr_config_aneg(phydev); + } +@@ -457,7 +458,9 @@ static int aqr107_read_status(struct phy_device *phydev) + } + + /* Read possibly downshifted rate from vendor register */ +- return aqr107_read_rate(phydev); ++ ret = aqr107_read_rate(phydev); ++ ++ return ret; + } + + static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) +-- +2.37.3 + |