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-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/9049-net-phy-aquantia-Added-support-for-AQR113-PHY-device.patch155
1 files changed, 155 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/9049-net-phy-aquantia-Added-support-for-AQR113-PHY-device.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/9049-net-phy-aquantia-Added-support-for-AQR113-PHY-device.patch
new file mode 100644
index 00000000..ea263d88
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/9049-net-phy-aquantia-Added-support-for-AQR113-PHY-device.patch
@@ -0,0 +1,155 @@
+From 2ef0d79e86eb36f61e98fd9ba62858c5d2689fd9 Mon Sep 17 00:00:00 2001
+From: rgaridap <Ramesh.Garidapuri@amd.com>
+Date: Thu, 2 Jun 2022 12:43:51 +0530
+Subject: [PATCH 49/57] net: phy: aquantia: Added support for AQR113 PHY device
+
+ Add support for AQR113 family
+
+Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com>
+Change-Id: Ifacb46293faec6282f41579744ebe2a61b25a19e
+---
+ drivers/net/phy/aquantia_main.c | 100 ++++++++++++++++++++++++++++++++
+ 1 file changed, 100 insertions(+)
+
+diff --git a/drivers/net/phy/aquantia_main.c b/drivers/net/phy/aquantia_main.c
+index 3221224525ac..f7c10d8fee1f 100644
+--- a/drivers/net/phy/aquantia_main.c
++++ b/drivers/net/phy/aquantia_main.c
+@@ -22,6 +22,7 @@
+ #define PHY_ID_AQR107 0x03a1b4e0
+ #define PHY_ID_AQCS109 0x03a1b5c2
+ #define PHY_ID_AQR405 0x03a1b4b0
++#define PHY_ID_AQR113 0x31c31c12
+
+ #define MDIO_PHYXS_VEND_IF_STATUS 0xe812
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
+@@ -255,6 +256,65 @@ static int aqr_config_aneg(struct phy_device *phydev)
+ return genphy_c45_check_and_restart_aneg(phydev, changed);
+ }
+
++
++static int aqr113_set_mode(struct phy_device *phydev)
++{
++
++ int val;
++ int fw;
++ int build;
++
++ fw = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
++ if (fw < 0)
++ return val;
++ val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
++ if (val < 0)
++ return val;
++
++ build = FIELD_GET(GENMASK(7,0), val);
++
++ if ((fw == 0x506) && (build = 0x16)) {
++
++ /* set PHY in SGMI mode for 1000M with system side AN disabled*/
++ val = phy_read_mmd(phydev, 0x7, 0xc400);
++ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->advertising))
++ val = val | (3 << 0xe);
++ else
++ val = val & (~( 3<< 0xe));
++ phy_write_mmd(phydev, 0x7, 0xc400,val);
++
++
++ /* set PHY in SGMI mode for 2500M with system side AN disabled */
++ val = phy_read_mmd(phydev, 0x7, 0xc400);
++ if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
++ val = val | (1 << 0xa);
++ else
++ val = val & (~( 1<< 0xa));
++ phy_write_mmd(phydev, 0x7, 0xc400,val);
++
++ /* clear 5G support */
++ val = phy_read_mmd(phydev, 0x7, 0xc400);
++ val = val & (~( 1<< 0xb));
++ phy_write_mmd(phydev, 0x7, 0xc400,val);
++
++
++ val = phy_read_mmd(phydev, 0x7, 0x20);
++ if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, phydev->advertising))
++ val = val | (1 << 0xc);
++ else
++ val = val & (~( 1<< 0xc));
++ phy_write_mmd(phydev, 0x7, 0x20,val);
++
++ }
++ return 0;
++}
++
++static int aqr113_config_aneg(struct phy_device *phydev)
++{
++ aqr113_set_mode(phydev);
++ return aqr_config_aneg(phydev);
++}
++
+ static int aqr_config_intr(struct phy_device *phydev)
+ {
+ bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
+@@ -529,6 +589,32 @@ static int aqr107_config_init(struct phy_device *phydev)
+ return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
+ }
+
++static int aqr113_config_init(struct phy_device *phydev)
++{
++ int ret;
++ int val;
++
++ /* Check that the PHY interface type is compatible */
++ if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
++ phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
++ phydev->interface != PHY_INTERFACE_MODE_10GBASER)
++ return -ENODEV;
++
++ WARN(phydev->interface == PHY_INTERFACE_MODE_10GKR,
++ "Your devicetree is out of date, please update it. The AQR113 family doesn't support 10GKR, maybe you mean 10GBASER.\n");
++
++ ret = aqr107_wait_reset_complete(phydev);
++ if (!ret)
++ aqr107_chip_info(phydev);
++
++ /* clear 5G support */
++ val = phy_read_mmd(phydev, 0x7, 0xc400);
++ val = val & (~( 1<< 0xb));
++ phy_write_mmd(phydev, 0x7, 0xc400,val);
++
++ return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
++}
++
+ static int aqcs109_config_init(struct phy_device *phydev)
+ {
+ int ret;
+@@ -673,6 +759,19 @@ static struct phy_driver aqr_driver[] = {
+ .get_stats = aqr107_get_stats,
+ .link_change_notify = aqr107_link_change_notify,
+ },
++
++{
++ PHY_ID_MATCH_MODEL(PHY_ID_AQR113),
++ .name = "Aquantia AQR113",
++ .probe = aqr107_probe,
++ .config_init = aqr113_config_init,
++ .config_aneg = aqr113_config_aneg,
++ .read_status = aqr107_read_status,
++ .suspend = aqr107_suspend,
++ .resume = aqr107_resume,
++ .get_stats = aqr107_get_stats,
++},
++
+ {
+ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
+ .name = "Aquantia AQCS109",
+@@ -709,6 +808,7 @@ static struct mdio_device_id __maybe_unused aqr_tbl[] = {
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
++ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
+ { }
+--
+2.37.3
+