diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0082-x86-cpufeatures-Add-virtual-TSC_AUX-feature-bit.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0082-x86-cpufeatures-Add-virtual-TSC_AUX-feature-bit.patch | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0082-x86-cpufeatures-Add-virtual-TSC_AUX-feature-bit.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0082-x86-cpufeatures-Add-virtual-TSC_AUX-feature-bit.patch new file mode 100644 index 00000000..d80a9235 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0082-x86-cpufeatures-Add-virtual-TSC_AUX-feature-bit.patch @@ -0,0 +1,41 @@ +From 8f03d4af74f086a9d8fefb4f51ee34176eda62bc Mon Sep 17 00:00:00 2001 +From: Babu Moger <babu.moger@amd.com> +Date: Tue, 19 Apr 2022 15:53:52 -0500 +Subject: [PATCH 82/86] x86/cpufeatures: Add virtual TSC_AUX feature bit + +commit f30903394eb62316dddea8801b357f5cec4df187 upstream + +The TSC_AUX Virtualization feature allows AMD SEV-ES guests to securely use +TSC_AUX (auxiliary time stamp counter data) MSR in RDTSCP and RDPID +instructions. + +The TSC_AUX MSR is typically initialized to APIC ID or another unique +identifier so that software can quickly associate returned TSC value +with the logical processor. + +Add the feature bit and also include it in the kvm for detection. + +Signed-off-by: Babu Moger <babu.moger@amd.com> +Acked-by: Borislav Petkov <bp@suse.de> +Message-Id: <165040157111.1399644.6123821125319995316.stgit@bmoger-ubuntu> +Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> +Signed-off-by: Zhaolong Zhang <zhaolong.zhang@windriver.com> +--- + arch/x86/include/asm/cpufeatures.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h +index 1db6a7bd51d6..ad146c4fe630 100644 +--- a/arch/x86/include/asm/cpufeatures.h ++++ b/arch/x86/include/asm/cpufeatures.h +@@ -409,6 +409,7 @@ + #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */ + #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */ + #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ ++#define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* Virtual TSC_AUX */ + #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ + + /* +-- +2.37.3 + |