diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0081-perf-x86-amd-core-Fix-reloading-events-for-SVM.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0081-perf-x86-amd-core-Fix-reloading-events-for-SVM.patch | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0081-perf-x86-amd-core-Fix-reloading-events-for-SVM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0081-perf-x86-amd-core-Fix-reloading-events-for-SVM.patch new file mode 100644 index 00000000..9e4a3095 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0081-perf-x86-amd-core-Fix-reloading-events-for-SVM.patch @@ -0,0 +1,80 @@ +From 709bf05167d31ee7bea9b07f63ab03e0da45b1f7 Mon Sep 17 00:00:00 2001 +From: Sandipan Das <sandipan.das@amd.com> +Date: Wed, 18 May 2022 14:13:27 +0530 +Subject: [PATCH 81/86] perf/x86/amd/core: Fix reloading events for SVM + +commit bae19fdd7e9e759580ac4693d2df3bc23ab415d7 upstream + +Commit 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only +counting with SVM disabled") addresses an issue in which the +Host-Only bit in the counter control registers needs to be +masked off when SVM is not enabled. + +The events need to be reloaded whenever SVM is enabled or +disabled for a CPU and this requires the PERF_CTL registers +to be reprogrammed using {enable,disable}_all(). However, +PerfMonV2 variants of these functions do not reprogram the +PERF_CTL registers. Hence, the legacy enable_all() function +should also be called. + +Fixes: 9622e67e3980 ("perf/x86/amd/core: Add PerfMonV2 counter control") +Reported-by: Like Xu <likexu@tencent.com> +Signed-off-by: Sandipan Das <sandipan.das@amd.com> +Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> +Link: https://lkml.kernel.org/r/20220518084327.464005-1-sandipan.das@amd.com +Signed-off-by: Zhaolong Zhang <zhaolong.zhang@windriver.com> +--- + arch/x86/events/amd/core.c | 24 ++++++++++++++++++++---- + 1 file changed, 20 insertions(+), 4 deletions(-) + +diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c +index 3eee59c64daa..9ac3718410ce 100644 +--- a/arch/x86/events/amd/core.c ++++ b/arch/x86/events/amd/core.c +@@ -1472,6 +1472,24 @@ __init int amd_pmu_init(void) + return 0; + } + ++static inline void amd_pmu_reload_virt(void) ++{ ++ if (x86_pmu.version >= 2) { ++ /* ++ * Clear global enable bits, reprogram the PERF_CTL ++ * registers with updated perf_ctr_virt_mask and then ++ * set global enable bits once again ++ */ ++ amd_pmu_v2_disable_all(); ++ amd_pmu_enable_all(0); ++ amd_pmu_v2_enable_all(0); ++ return; ++ } ++ ++ amd_pmu_disable_all(); ++ amd_pmu_enable_all(0); ++} ++ + void amd_pmu_enable_virt(void) + { + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); +@@ -1479,8 +1497,7 @@ void amd_pmu_enable_virt(void) + cpuc->perf_ctr_virt_mask = 0; + + /* Reload all events */ +- amd_pmu_disable_all(); +- x86_pmu_enable_all(0); ++ amd_pmu_reload_virt(); + } + EXPORT_SYMBOL_GPL(amd_pmu_enable_virt); + +@@ -1497,7 +1514,6 @@ void amd_pmu_disable_virt(void) + cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY; + + /* Reload all events */ +- amd_pmu_disable_all(); +- x86_pmu_enable_all(0); ++ amd_pmu_reload_virt(); + } + EXPORT_SYMBOL_GPL(amd_pmu_disable_virt); +-- +2.37.3 + |