diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0079-perf-x86-amd-Fix-AMD-BRS-period-adjustment.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0079-perf-x86-amd-Fix-AMD-BRS-period-adjustment.patch | 122 |
1 files changed, 122 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0079-perf-x86-amd-Fix-AMD-BRS-period-adjustment.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0079-perf-x86-amd-Fix-AMD-BRS-period-adjustment.patch new file mode 100644 index 00000000..3e8eca9d --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0079-perf-x86-amd-Fix-AMD-BRS-period-adjustment.patch @@ -0,0 +1,122 @@ +From 6a9fdabf0e988a5010bec70307180ad6dfa2b0d1 Mon Sep 17 00:00:00 2001 +From: Peter Zijlstra <peterz@infradead.org> +Date: Tue, 10 May 2022 21:22:04 +0200 +Subject: [PATCH 79/86] perf/x86/amd: Fix AMD BRS period adjustment + +commit 3c27b0c6ea48bc61492a138c410e262735d660ab upstream + +There's two problems with the current amd_brs_adjust_period() code: + + - it isn't in fact AMD specific and wil always adjust the period; + + - it adjusts the period, while it should only adjust the event count, + resulting in repoting a short period. + +Fix this by using x86_pmu.limit_period, this makes it specific to the +AMD BRS case and ensures only the event count is adjusted while the +reported period is unmodified. + +Fixes: ba2fe7500845 ("perf/x86/amd: Add AMD branch sampling period adjustment") +Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> +Signed-off-by: Zhaolong Zhang <zhaolong.zhang@windriver.com> +--- + arch/x86/events/amd/core.c | 13 +++++++++++++ + arch/x86/events/core.c | 7 ------- + arch/x86/events/perf_event.h | 18 ------------------ + 3 files changed, 13 insertions(+), 25 deletions(-) + +diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c +index d81eac2284ea..3eee59c64daa 100644 +--- a/arch/x86/events/amd/core.c ++++ b/arch/x86/events/amd/core.c +@@ -1255,6 +1255,18 @@ static void amd_pmu_sched_task(struct perf_event_context *ctx, + amd_pmu_brs_sched_task(ctx, sched_in); + } + ++static u64 amd_pmu_limit_period(struct perf_event *event, u64 left) ++{ ++ /* ++ * Decrease period by the depth of the BRS feature to get the last N ++ * taken branches and approximate the desired period ++ */ ++ if (has_branch_stack(event) && left > x86_pmu.lbr_nr) ++ left -= x86_pmu.lbr_nr; ++ ++ return left; ++} ++ + static __initconst const struct x86_pmu amd_pmu = { + .name = "AMD", + .handle_irq = amd_pmu_handle_irq, +@@ -1415,6 +1427,7 @@ static int __init amd_core_pmu_init(void) + if (boot_cpu_data.x86 >= 0x19 && !amd_brs_init()) { + x86_pmu.get_event_constraints = amd_get_event_constraints_f19h; + x86_pmu.sched_task = amd_pmu_sched_task; ++ x86_pmu.limit_period = amd_pmu_limit_period; + /* + * put_event_constraints callback same as Fam17h, set above + */ +diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c +index fcc25b4783a3..1ea82bb2639b 100644 +--- a/arch/x86/events/core.c ++++ b/arch/x86/events/core.c +@@ -1370,13 +1370,6 @@ int x86_perf_event_set_period(struct perf_event *event) + x86_pmu.set_topdown_event_period) + return x86_pmu.set_topdown_event_period(event); + +- /* +- * decrease period by the depth of the BRS feature to get +- * the last N taken branches and approximate the desired period +- */ +- if (has_branch_stack(event)) +- period = amd_brs_adjust_period(period); +- + /* + * If we are way outside a reasonable range then just skip forward: + */ +diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h +index 49948372b44a..aa53815c2f61 100644 +--- a/arch/x86/events/perf_event.h ++++ b/arch/x86/events/perf_event.h +@@ -1252,14 +1252,6 @@ static inline void amd_pmu_brs_del(struct perf_event *event) + } + + void amd_pmu_brs_sched_task(struct perf_event_context *ctx, bool sched_in); +- +-static inline s64 amd_brs_adjust_period(s64 period) +-{ +- if (period > x86_pmu.lbr_nr) +- return period - x86_pmu.lbr_nr; +- +- return period; +-} + #else + static inline int amd_brs_init(void) + { +@@ -1288,11 +1280,6 @@ static inline void amd_pmu_brs_sched_task(struct perf_event_context *ctx, bool s + { + } + +-static inline s64 amd_brs_adjust_period(s64 period) +-{ +- return period; +-} +- + static inline void amd_brs_enable_all(void) + { + } +@@ -1322,11 +1309,6 @@ static inline void amd_brs_enable_all(void) + static inline void amd_brs_disable_all(void) + { + } +- +-static inline s64 amd_brs_adjust_period(s64 period) +-{ +- return period; +-} + #endif /* CONFIG_CPU_SUP_AMD */ + + static inline int is_pebs_pt(struct perf_event *event) +-- +2.37.3 + |