diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0072-perf-x86-amd-core-Detect-available-counters.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0072-perf-x86-amd-core-Detect-available-counters.patch | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0072-perf-x86-amd-core-Detect-available-counters.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0072-perf-x86-amd-core-Detect-available-counters.patch new file mode 100644 index 00000000..0ce157b6 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0072-perf-x86-amd-core-Detect-available-counters.patch @@ -0,0 +1,86 @@ +From 21e62a82997c18eb4d417350753ee242821ea972 Mon Sep 17 00:00:00 2001 +From: Sandipan Das <sandipan.das@amd.com> +Date: Thu, 21 Apr 2022 11:16:56 +0530 +Subject: [PATCH 72/86] perf/x86/amd/core: Detect available counters + +commit 56e026a7ca3f92b8e44359e1f705febd1833f701 upstream + +If AMD Performance Monitoring Version 2 (PerfMonV2) is +supported, use CPUID leaf 0x80000022 EBX to detect the +number of Core PMCs. This offers more flexibility if the +counts change in later processor families. + +Signed-off-by: Sandipan Das <sandipan.das@amd.com> +Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> +Link: https://lkml.kernel.org/r/68a6d9688df189267db26530378870edd34f7b06.1650515382.git.sandipan.das@amd.com +Signed-off-by: Zhaolong Zhang <zhaolong.zhang@windriver.com> +--- + arch/x86/events/amd/core.c | 6 ++++++ + arch/x86/include/asm/perf_event.h | 17 +++++++++++++++++ + 2 files changed, 23 insertions(+) + +diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c +index b70dfa028ba5..52fd7941a724 100644 +--- a/arch/x86/events/amd/core.c ++++ b/arch/x86/events/amd/core.c +@@ -1186,6 +1186,7 @@ static const struct attribute_group *amd_attr_update[] = { + + static int __init amd_core_pmu_init(void) + { ++ union cpuid_0x80000022_ebx ebx; + u64 even_ctr_mask = 0ULL; + int i; + +@@ -1206,9 +1207,14 @@ static int __init amd_core_pmu_init(void) + + /* Check for Performance Monitoring v2 support */ + if (boot_cpu_has(X86_FEATURE_PERFMON_V2)) { ++ ebx.full = cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES); ++ + /* Update PMU version for later usage */ + x86_pmu.version = 2; + ++ /* Find the number of available Core PMCs */ ++ x86_pmu.num_counters = ebx.split.num_core_pmc; ++ + amd_pmu_global_cntr_mask = (1ULL << x86_pmu.num_counters) - 1; + } + +diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h +index 0e72770c45ff..92d72a4db57b 100644 +--- a/arch/x86/include/asm/perf_event.h ++++ b/arch/x86/include/asm/perf_event.h +@@ -186,6 +186,18 @@ union cpuid28_ecx { + unsigned int full; + }; + ++/* ++ * AMD "Extended Performance Monitoring and Debug" CPUID ++ * detection/enumeration details: ++ */ ++union cpuid_0x80000022_ebx { ++ struct { ++ /* Number of Core Performance Counters */ ++ unsigned int num_core_pmc:4; ++ } split; ++ unsigned int full; ++}; ++ + struct x86_pmu_capability { + int version; + int num_counters_gp; +@@ -372,6 +384,11 @@ struct pebs_xmm { + u64 xmm[16*2]; /* two entries for each register */ + }; + ++/* ++ * AMD Extended Performance Monitoring and Debug cpuid feature detection ++ */ ++#define EXT_PERFMON_DEBUG_FEATURES 0x80000022 ++ + /* + * IBS cpuid feature detection + */ +-- +2.37.3 + |