diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0070-x86-msr-Add-PerfCntrGlobal-registers.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0070-x86-msr-Add-PerfCntrGlobal-registers.patch | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0070-x86-msr-Add-PerfCntrGlobal-registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0070-x86-msr-Add-PerfCntrGlobal-registers.patch new file mode 100644 index 00000000..6f05845c --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0070-x86-msr-Add-PerfCntrGlobal-registers.patch @@ -0,0 +1,50 @@ +From a4dfc3b9a600e737446dcaf18952fe7c74f3b7ea Mon Sep 17 00:00:00 2001 +From: Sandipan Das <sandipan.das@amd.com> +Date: Thu, 21 Apr 2022 11:16:54 +0530 +Subject: [PATCH 70/86] x86/msr: Add PerfCntrGlobal* registers + +commit 089be16d5992dd0bc6df15ef12042fd1023ded9a upstream + +Add MSR definitions that will be used to enable the new AMD +Performance Monitoring Version 2 (PerfMonV2) features. These +include: + + * Performance Counter Global Control (PerfCntrGlobalCtl) + * Performance Counter Global Status (PerfCntrGlobalStatus) + * Performance Counter Global Status Clear (PerfCntrGlobalStatusClr) + +The new Performance Counter Global Control and Status MSRs +provide an interface for enabling or disabling multiple +counters at the same time and for testing overflow without +probing the individual registers for each PMC. + +The availability of these registers is indicated through the +PerfMonV2 feature bit of CPUID leaf 0x80000022 EAX. + +Signed-off-by: Sandipan Das <sandipan.das@amd.com> +Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> +Link: https://lkml.kernel.org/r/cdc0d8f75bd519848731b5c64d924f5a0619a573.1650515382.git.sandipan.das@amd.com +Signed-off-by: Zhaolong Zhang <zhaolong.zhang@windriver.com> +--- + arch/x86/include/asm/msr-index.h | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h +index 480e4870aa42..9629a054c199 100644 +--- a/arch/x86/include/asm/msr-index.h ++++ b/arch/x86/include/asm/msr-index.h +@@ -542,6 +542,11 @@ + #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) + #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) + ++/* AMD Performance Counter Global Status and Control MSRs */ ++#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 ++#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 ++#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 ++ + /* Fam 17h MSRs */ + #define MSR_F17H_IRPERF 0xc00000e9 + +-- +2.37.3 + |