diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0069-x86-cpufeatures-Add-PerfMonV2-feature-bit.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0069-x86-cpufeatures-Add-PerfMonV2-feature-bit.patch | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0069-x86-cpufeatures-Add-PerfMonV2-feature-bit.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0069-x86-cpufeatures-Add-PerfMonV2-feature-bit.patch new file mode 100644 index 00000000..6abf9476 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0069-x86-cpufeatures-Add-PerfMonV2-feature-bit.patch @@ -0,0 +1,57 @@ +From 26f8e6b4feed94c2b7abd7b9e3d9511d5166eb80 Mon Sep 17 00:00:00 2001 +From: Sandipan Das <sandipan.das@amd.com> +Date: Thu, 21 Apr 2022 11:16:53 +0530 +Subject: [PATCH 69/86] x86/cpufeatures: Add PerfMonV2 feature bit + +commit d6d0c7f681fda1d07e005c8f653e578b77a0eb40 upstream + +CPUID leaf 0x80000022 i.e. ExtPerfMonAndDbg advertises some +new performance monitoring features for AMD processors. + +Bit 0 of EAX indicates support for Performance Monitoring +Version 2 (PerfMonV2) features. If found to be set during +PMU initialization, the EBX bits of the same CPUID function +can be used to determine the number of available PMCs for +different PMU types. Additionally, Core PMCs can be managed +using new global control and status registers. + +For better utilization of feature words, PerfMonV2 is added +as a scattered feature bit. + +Signed-off-by: Sandipan Das <sandipan.das@amd.com> +Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> +Link: https://lkml.kernel.org/r/c70e497e22f18e7f05b025bb64ca21cc12b17792.1650515382.git.sandipan.das@amd.com +Signed-off-by: Zhaolong Zhang <zhaolong.zhang@windriver.com> +--- + arch/x86/include/asm/cpufeatures.h | 2 +- + arch/x86/kernel/cpu/scattered.c | 1 + + 2 files changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h +index 4ae869607697..1db6a7bd51d6 100644 +--- a/arch/x86/include/asm/cpufeatures.h ++++ b/arch/x86/include/asm/cpufeatures.h +@@ -211,7 +211,7 @@ + #define X86_FEATURE_SSBD ( 7*32+17) /* Speculative Store Bypass Disable */ + #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ + #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */ +-/* FREE! ( 7*32+20) */ ++#define X86_FEATURE_PERFMON_V2 ( 7*32+20) /* AMD Performance Monitoring Version 2 */ + #define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */ + #define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */ + #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */ +diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c +index 06bfef1c4175..c0cdd8ddde66 100644 +--- a/arch/x86/kernel/cpu/scattered.c ++++ b/arch/x86/kernel/cpu/scattered.c +@@ -43,6 +43,7 @@ static const struct cpuid_bit cpuid_bits[] = { + { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, + { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, + { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, ++ { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, + { 0, 0, 0, 0, 0 } + }; + +-- +2.37.3 + |