diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0054-x86-cpufeatures-Add-AMD-Collaborative-Processor-Perf.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0054-x86-cpufeatures-Add-AMD-Collaborative-Processor-Perf.patch | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0054-x86-cpufeatures-Add-AMD-Collaborative-Processor-Perf.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0054-x86-cpufeatures-Add-AMD-Collaborative-Processor-Perf.patch new file mode 100644 index 00000000..0c1c511a --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/0054-x86-cpufeatures-Add-AMD-Collaborative-Processor-Perf.patch @@ -0,0 +1,40 @@ +From ea860095231253ca7a4d06919918a281998f1f27 Mon Sep 17 00:00:00 2001 +From: Huang Rui <ray.huang@amd.com> +Date: Fri, 24 Dec 2021 09:04:55 +0800 +Subject: [PATCH 54/86] x86/cpufeatures: Add AMD Collaborative Processor + Performance Control feature flag + +commit d341db8f48ea43314f489921962c7f8f4ec27239 upstream + +Add Collaborative Processor Performance Control feature flag for AMD +processors. + +This feature flag will be used on the following AMD P-State driver. The +AMD P-State driver has two approaches to implement the frequency control +behavior. That depends on the CPU hardware implementation. One is "Full +MSR Support" and another is "Shared Memory Support". The feature flag +indicates the current processors with "Full MSR Support". + +Acked-by: Borislav Petkov <bp@suse.de> +Signed-off-by: Huang Rui <ray.huang@amd.com> +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> +Signed-off-by: Zhaolong Zhang <zhaolong.zhang@windriver.com> +--- + arch/x86/include/asm/cpufeatures.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h +index 2b56bfef9917..ebe6666bbc71 100644 +--- a/arch/x86/include/asm/cpufeatures.h ++++ b/arch/x86/include/asm/cpufeatures.h +@@ -321,6 +321,7 @@ + #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ + #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ + #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ ++#define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */ + #define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */ + + /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ +-- +2.37.3 + |