diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4585-drm-amd-powerplay-read-pcie-speed-width-info-v2.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4585-drm-amd-powerplay-read-pcie-speed-width-info-v2.patch | 214 |
1 files changed, 214 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4585-drm-amd-powerplay-read-pcie-speed-width-info-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4585-drm-amd-powerplay-read-pcie-speed-width-info-v2.patch new file mode 100644 index 00000000..72664fbb --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4585-drm-amd-powerplay-read-pcie-speed-width-info-v2.patch @@ -0,0 +1,214 @@ +From 1eb88c64a5d5fa596fc96e37b5f72e79a7da6064 Mon Sep 17 00:00:00 2001 +From: Kenneth Feng <kenneth.feng@amd.com> +Date: Tue, 12 Nov 2019 16:27:11 +0800 +Subject: [PATCH 4585/4736] drm/amd/powerplay: read pcie speed/width info (v2) + +sysfs interface to read pcie speed&width info on navi1x. + +v2: fix warning (trivial) + +Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> +Reviewed-by: Evan Quan <evan.quan@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 10 ++-- + drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 8 +++ + drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 57 +++++++++++++++++-- + drivers/gpu/drm/amd/powerplay/navi10_ppt.h | 3 + + 4 files changed, 69 insertions(+), 9 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +index d5335bdc709b..acbbafeea01c 100644 +--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +@@ -1081,10 +1081,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu, + return ret; + + if (adev->asic_type != CHIP_ARCTURUS) { +- ret = smu_override_pcie_parameters(smu); +- if (ret) +- return ret; +- + ret = smu_notify_display_change(smu); + if (ret) + return ret; +@@ -1113,6 +1109,12 @@ static int smu_smc_table_hw_init(struct smu_context *smu, + return ret; + } + ++ if (adev->asic_type != CHIP_ARCTURUS) { ++ ret = smu_override_pcie_parameters(smu); ++ if (ret) ++ return ret; ++ } ++ + ret = smu_set_default_od_settings(smu, initialize); + if (ret) + return ret; +diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h +index ebdf7bd79a67..716fcb274191 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h +@@ -49,6 +49,8 @@ + + #define SMU11_TOOL_SIZE 0x19000 + ++#define MAX_PCIE_CONF 2 ++ + #define CLK_MAP(clk, index) \ + [SMU_##clk] = {1, (index)} + +@@ -89,6 +91,11 @@ struct smu_11_0_dpm_table { + uint32_t max; /* MHz */ + }; + ++struct smu_11_0_pcie_table { ++ uint8_t pcie_gen[MAX_PCIE_CONF]; ++ uint8_t pcie_lane[MAX_PCIE_CONF]; ++}; ++ + struct smu_11_0_dpm_tables { + struct smu_11_0_dpm_table soc_table; + struct smu_11_0_dpm_table gfx_table; +@@ -101,6 +108,7 @@ struct smu_11_0_dpm_tables { + struct smu_11_0_dpm_table display_table; + struct smu_11_0_dpm_table phy_table; + struct smu_11_0_dpm_table fclk_table; ++ struct smu_11_0_pcie_table pcie_table; + }; + + struct smu_11_0_dpm_context { +diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +index aca913289e3c..c94c2b67c309 100644 +--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c ++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +@@ -35,6 +35,7 @@ + #include "navi10_ppt.h" + #include "smu_v11_0_pptable.h" + #include "smu_v11_0_ppsmc.h" ++#include "nbio/nbio_7_4_sh_mask.h" + + #include "asic_reg/mp/mp_11_0_sh_mask.h" + +@@ -600,6 +601,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) + struct smu_table_context *table_context = &smu->smu_table; + struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; + PPTable_t *driver_ppt = NULL; ++ int i; + + driver_ppt = table_context->driver_pptable; + +@@ -630,6 +632,11 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) + dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0]; + dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1]; + ++ for (i = 0; i < MAX_PCIE_CONF; i++) { ++ dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i]; ++ dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i]; ++ } ++ + return 0; + } + +@@ -726,16 +733,20 @@ static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_tabl + static int navi10_print_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf) + { +- OverDriveTable_t *od_table; +- struct smu_11_0_overdrive_table *od_settings; + uint16_t *curve_settings; + int i, size = 0, ret = 0; + uint32_t cur_value = 0, value = 0, count = 0; + uint32_t freq_values[3] = {0}; + uint32_t mark_index = 0; + struct smu_table_context *table_context = &smu->smu_table; +- od_table = (OverDriveTable_t *)table_context->overdrive_table; +- od_settings = smu->od_settings; ++ uint32_t gen_speed, lane_width; ++ struct smu_dpm_context *smu_dpm = &smu->smu_dpm; ++ struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; ++ struct amdgpu_device *adev = smu->adev; ++ PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; ++ OverDriveTable_t *od_table = ++ (OverDriveTable_t *)table_context->overdrive_table; ++ struct smu_11_0_overdrive_table *od_settings = smu->od_settings; + + switch (clk_type) { + case SMU_GFXCLK: +@@ -786,6 +797,30 @@ static int navi10_print_clk_levels(struct smu_context *smu, + + } + break; ++ case SMU_PCIE: ++ gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & ++ PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) ++ >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; ++ lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & ++ PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) ++ >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; ++ for (i = 0; i < NUM_LINK_LEVELS; i++) ++ size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i, ++ (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : ++ (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : ++ (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : ++ (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", ++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : ++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : ++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : ++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : ++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : ++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", ++ pptable->LclkFreq[i], ++ (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && ++ (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? ++ "*" : ""); ++ break; + case SMU_OD_SCLK: + if (!smu->od_enabled || !od_table || !od_settings) + break; +@@ -1722,6 +1757,9 @@ static int navi10_update_pcie_parameters(struct smu_context *smu, + int ret, i; + uint32_t smu_pcie_arg; + ++ struct smu_dpm_context *smu_dpm = &smu->smu_dpm; ++ struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; ++ + for (i = 0; i < NUM_LINK_LEVELS; i++) { + smu_pcie_arg = (i << 16) | + ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) : +@@ -1730,8 +1768,17 @@ static int navi10_update_pcie_parameters(struct smu_context *smu, + ret = smu_send_smc_msg_with_param(smu, + SMU_MSG_OverridePcieParameters, + smu_pcie_arg); ++ ++ if (ret) ++ return ret; ++ ++ if (pptable->PcieGenSpeed[i] > pcie_gen_cap) ++ dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; ++ if (pptable->PcieLaneCount[i] > pcie_width_cap) ++ dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; + } +- return ret; ++ ++ return 0; + } + + static inline void navi10_dump_od_table(OverDriveTable_t *od_table) { +diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h +index fd6dda1a67a1..ec03c7992f6d 100644 +--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h ++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h +@@ -35,6 +35,9 @@ + + #define NAVI10_VOLTAGE_SCALE (4) + ++#define smnPCIE_LC_SPEED_CNTL 0x11140290 ++#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 ++ + extern void navi10_set_ppt_funcs(struct smu_context *smu); + + #endif +-- +2.17.1 + |