diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3808-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3808-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch | 189 |
1 files changed, 189 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3808-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3808-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch new file mode 100644 index 00000000..2db39b10 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3808-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch @@ -0,0 +1,189 @@ +From 34a2a6a4fee196cb732c921ffc86e560c3183408 Mon Sep 17 00:00:00 2001 +From: Monk Liu <Monk.Liu@amd.com> +Date: Wed, 31 Jul 2019 16:47:56 +0800 +Subject: [PATCH 3808/4256] drm/amdgpu: fix double ucode load by PSP(v3) + +previously the ucode loading of PSP was repreated, one executed in +phase_1 init/re-init/resume and the other in fw_loading routine + +Avoid this double loading by clearing ip_blocks.status.hw in suspend or reset +prior to the FW loading and any block's hw_init/resume + +v2: +still do the smu fw loading since it is needed by bare-metal + +v3: +drop the change in reinit_early_sriov, just clear all block's status.hw +in the head place and set the status.hw after hw_init done is enough + +Change-Id: I3b871124da60ff356a78ea974ed6cd2b7e750376 +Signed-off-by: Monk Liu <Monk.Liu@amd.com> +Reviewed-by: Emily Deng <Emily.Deng@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 68 +++++++++++++--------- + 1 file changed, 42 insertions(+), 26 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index d3152aa16396..74c7723ad5e2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -1723,28 +1723,34 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev) + + if (adev->asic_type >= CHIP_VEGA10) { + for (i = 0; i < adev->num_ip_blocks; i++) { +- if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { +- if (adev->in_gpu_reset || adev->in_suspend) { +- if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) +- break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */ +- r = adev->ip_blocks[i].version->funcs->resume(adev); +- if (r) { +- DRM_ERROR("resume of IP block <%s> failed %d\n", ++ if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP) ++ continue; ++ ++ /* no need to do the fw loading again if already done*/ ++ if (adev->ip_blocks[i].status.hw == true) ++ break; ++ ++ if (adev->in_gpu_reset || adev->in_suspend) { ++ r = adev->ip_blocks[i].version->funcs->resume(adev); ++ if (r) { ++ DRM_ERROR("resume of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); +- return r; +- } +- } else { +- r = adev->ip_blocks[i].version->funcs->hw_init(adev); +- if (r) { +- DRM_ERROR("hw_init of IP block <%s> failed %d\n", +- adev->ip_blocks[i].version->funcs->name, r); +- return r; +- } ++ return r; ++ } ++ } else { ++ r = adev->ip_blocks[i].version->funcs->hw_init(adev); ++ if (r) { ++ DRM_ERROR("hw_init of IP block <%s> failed %d\n", ++ adev->ip_blocks[i].version->funcs->name, r); ++ return r; + } +- adev->ip_blocks[i].status.hw = true; + } ++ ++ adev->ip_blocks[i].status.hw = true; ++ break; + } + } ++ + r = amdgpu_pm_load_smu_firmware(adev, &smu_version); + + return r; +@@ -2178,7 +2184,9 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) + if (r) { + DRM_ERROR("suspend of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); ++ return r; + } ++ adev->ip_blocks[i].status.hw = false; + } + } + +@@ -2219,15 +2227,16 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) + if (is_support_sw_smu(adev)) { + r = smu_set_mp1_state(&adev->smu, adev->mp1_state); + } else if (adev->powerplay.pp_funcs && +- adev->powerplay.pp_funcs->set_mp1_state) { ++ adev->powerplay.pp_funcs->set_mp1_state) { + r = adev->powerplay.pp_funcs->set_mp1_state( + adev->powerplay.pp_handle, + adev->mp1_state); +- } +- if (r) { +- DRM_ERROR("SMC failed to set mp1 state %d, %d\n", +- adev->mp1_state, r); +- return r; ++ if (r) { ++ DRM_ERROR("SMC failed to set mp1 state %d, %d\n", ++ adev->mp1_state, r); ++ return r; ++ } ++ adev->ip_blocks[i].status.hw = false; + } + } + +@@ -2284,6 +2293,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) + for (j = 0; j < adev->num_ip_blocks; j++) { + block = &adev->ip_blocks[j]; + ++ block->status.hw = false; + if (block->version->type != ip_order[i] || + !block->status.valid) + continue; +@@ -2292,6 +2302,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) + DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); + if (r) + return r; ++ block->status.hw = true; + } + } + +@@ -2319,13 +2330,15 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) + block = &adev->ip_blocks[j]; + + if (block->version->type != ip_order[i] || +- !block->status.valid) ++ !block->status.valid || ++ block->status.hw) + continue; + + r = block->version->funcs->hw_init(adev); + DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); + if (r) + return r; ++ block->status.hw = true; + } + } + +@@ -2349,17 +2362,19 @@ static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) + int i, r; + + for (i = 0; i < adev->num_ip_blocks; i++) { +- if (!adev->ip_blocks[i].status.valid) ++ if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) + continue; + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { ++ + r = adev->ip_blocks[i].version->funcs->resume(adev); + if (r) { + DRM_ERROR("resume of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); + return r; + } ++ adev->ip_blocks[i].status.hw = true; + } + } + +@@ -2384,7 +2399,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) + int i, r; + + for (i = 0; i < adev->num_ip_blocks; i++) { +- if (!adev->ip_blocks[i].status.valid) ++ if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) + continue; + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || +@@ -2397,6 +2412,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) + adev->ip_blocks[i].version->funcs->name, r); + return r; + } ++ adev->ip_blocks[i].status.hw = true; + } + + return 0; +-- +2.17.1 + |