diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3788-drm-amdgpu-For-Navi12-SRIOV-VF-register-mailbox-func.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3788-drm-amdgpu-For-Navi12-SRIOV-VF-register-mailbox-func.patch | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3788-drm-amdgpu-For-Navi12-SRIOV-VF-register-mailbox-func.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3788-drm-amdgpu-For-Navi12-SRIOV-VF-register-mailbox-func.patch new file mode 100644 index 00000000..1b641d1f --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3788-drm-amdgpu-For-Navi12-SRIOV-VF-register-mailbox-func.patch @@ -0,0 +1,73 @@ +From db8ca3585d94b3285d6c8df7fcbb9f26186f722c Mon Sep 17 00:00:00 2001 +From: Jiange Zhao <Jiange.Zhao@amd.com> +Date: Wed, 11 Sep 2019 17:29:07 +0800 +Subject: [PATCH 3788/4256] drm/amdgpu: For Navi12 SRIOV VF, register mailbox + functions + +Mailbox functions and interrupts are only for Navi12 VF. + +Register functions and irqs during initialization. + +Reviewed-by: Emily Deng <Emily.Deng@amd.com> +Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/nv.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c +index a61f43c0c9df..4c24672be12a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/nv.c ++++ b/drivers/gpu/drm/amd/amdgpu/nv.c +@@ -53,6 +53,7 @@ + #include "vcn_v2_0.h" + #include "dce_virtual.h" + #include "mes_v10_1.h" ++#include "mxgpu_nv.h" + + static const struct amd_ip_funcs nv_common_ip_funcs; + +@@ -426,6 +427,9 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) + + adev->nbio.funcs->detect_hw_virt(adev); + ++ if (amdgpu_sriov_vf(adev)) ++ adev->virt.ops = &xgpu_nv_virt_ops; ++ + switch (adev->asic_type) { + case CHIP_NAVI10: + case CHIP_NAVI14: +@@ -666,16 +670,31 @@ static int nv_common_early_init(void *handle) + return -EINVAL; + } + ++ if (amdgpu_sriov_vf(adev)) { ++ amdgpu_virt_init_setting(adev); ++ xgpu_nv_mailbox_set_irq_funcs(adev); ++ } ++ + return 0; + } + + static int nv_common_late_init(void *handle) + { ++ struct amdgpu_device *adev = (struct amdgpu_device *)handle; ++ ++ if (amdgpu_sriov_vf(adev)) ++ xgpu_nv_mailbox_get_irq(adev); ++ + return 0; + } + + static int nv_common_sw_init(void *handle) + { ++ struct amdgpu_device *adev = (struct amdgpu_device *)handle; ++ ++ if (amdgpu_sriov_vf(adev)) ++ xgpu_nv_mailbox_add_irq_id(adev); ++ + return 0; + } + +-- +2.17.1 + |