diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3142-drm-amd-amdgpu-vcn_v2_0-Mark-RB-commands-as-KMD-comm.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3142-drm-amd-amdgpu-vcn_v2_0-Mark-RB-commands-as-KMD-comm.patch | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3142-drm-amd-amdgpu-vcn_v2_0-Mark-RB-commands-as-KMD-comm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3142-drm-amd-amdgpu-vcn_v2_0-Mark-RB-commands-as-KMD-comm.patch new file mode 100644 index 00000000..790caf57 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3142-drm-amd-amdgpu-vcn_v2_0-Mark-RB-commands-as-KMD-comm.patch @@ -0,0 +1,94 @@ +From 2649ecb6a221c7a60c9b3aa1ae71ce58a780f0d0 Mon Sep 17 00:00:00 2001 +From: Thong Thai <thong.thai@amd.com> +Date: Thu, 25 Jul 2019 11:21:58 -0400 +Subject: [PATCH 3142/4256] drm/amd/amdgpu/vcn_v2_0: Mark RB commands as KMD + commands +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This +bit was previously set by the RBC HW on older firmware. Newer firmware +uses a SW RBC and this bit has to be set by the driver. + +Signed-off-by: Thong Thai <thong.thai@amd.com> +Reviewed-by: Leo Liu <leo.liu@amd.com> +Reviewed-by: Christian König <christian.koenig@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 + + drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 12 ++++++------ + 2 files changed, 7 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +index 38f0d53a6381..dface275c81a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +@@ -35,6 +35,7 @@ + #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0) + #define AMDGPU_VCN_HARVEST_VCN1 (1 << 1) + ++#define VCN_DEC_KMD_CMD 0x80000000 + #define VCN_DEC_CMD_FENCE 0x00000000 + #define VCN_DEC_CMD_TRAP 0x00000001 + #define VCN_DEC_CMD_WRITE_REG 0x00000004 +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +index 88e3dedcf926..800db1f297f6 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +@@ -1494,7 +1494,7 @@ void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) + amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); +- amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); ++ amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); + } + + /** +@@ -1509,7 +1509,7 @@ void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) + struct amdgpu_device *adev = ring->adev; + + amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); +- amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); ++ amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); + } + + /** +@@ -1556,7 +1556,7 @@ void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, + amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); + + amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); +- amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); ++ amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1)); + + amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); + amdgpu_ring_write(ring, 0); +@@ -1566,7 +1566,7 @@ void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, + + amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); + +- amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); ++ amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1)); + } + + /** +@@ -1612,7 +1612,7 @@ void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, + + amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); + +- amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); ++ amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1)); + } + + void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, +@@ -1643,7 +1643,7 @@ void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, + + amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); + +- amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); ++ amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1)); + } + + /** +-- +2.17.1 + |