diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3702-drm-amdgpu-Clean-sdma-wptr-register-when-only-enable.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3702-drm-amdgpu-Clean-sdma-wptr-register-when-only-enable.patch | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3702-drm-amdgpu-Clean-sdma-wptr-register-when-only-enable.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3702-drm-amdgpu-Clean-sdma-wptr-register-when-only-enable.patch new file mode 100644 index 00000000..7e525a36 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3702-drm-amdgpu-Clean-sdma-wptr-register-when-only-enable.patch @@ -0,0 +1,44 @@ +From f82b93188a20c1ace28b0acbf6d87253c320bdf7 Mon Sep 17 00:00:00 2001 +From: Emily Deng <Emily.Deng@amd.com> +Date: Wed, 7 Mar 2018 09:47:43 +0800 +Subject: [PATCH 3702/4131] drm/amdgpu: Clean sdma wptr register when only + enable wptr polling + +The sdma wptr polling memory is not fast enough, then the sdma +wptr register will be random, and not equal to sdma rptr, which +will cause sdma engine hang when load driver, so clean up the sdma +wptr directly to fix this issue. + +v2:add comment above the code and correct coding style +Signed-off-by: Emily Deng <Emily.Deng@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +index b9d857d..5a4f3c8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +@@ -719,14 +719,17 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) + WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], + upper_32_bits(wptr_gpu_addr)); + wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); +- if (ring->use_pollmem) ++ if (ring->use_pollmem) { ++ /*wptr polling is not enogh fast, directly clean the wptr register */ ++ WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); + wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, + SDMA0_GFX_RB_WPTR_POLL_CNTL, + ENABLE, 1); +- else ++ } else { + wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, + SDMA0_GFX_RB_WPTR_POLL_CNTL, + ENABLE, 0); ++ } + WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); + + /* enable DMA RB */ +-- +2.7.4 + |