diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0730-drm-amd-display-fix-dlg-ttu-calculation-input.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0730-drm-amd-display-fix-dlg-ttu-calculation-input.patch | 92 |
1 files changed, 92 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0730-drm-amd-display-fix-dlg-ttu-calculation-input.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0730-drm-amd-display-fix-dlg-ttu-calculation-input.patch new file mode 100644 index 00000000..6aa1460a --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0730-drm-amd-display-fix-dlg-ttu-calculation-input.patch @@ -0,0 +1,92 @@ +From 3844f59365877682b445b41f7a6dd08d5231c15d Mon Sep 17 00:00:00 2001 +From: Charlene Liu <charlene.liu@amd.com> +Date: Tue, 1 Aug 2017 21:13:24 -0400 +Subject: [PATCH 0730/4131] drm/amd/display: fix dlg ttu calculation input + +Signed-off-by: Charlene Liu <charlene.liu@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 37 ++++++++++++++++++++++-- + 1 file changed, 34 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +index 13b7d887..67da973 100644 +--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c ++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +@@ -401,7 +401,8 @@ static void pipe_ctx_to_e2e_pipe_params ( + static void dcn_bw_calc_rq_dlg_ttu( + const struct core_dc *dc, + const struct dcn_bw_internal_vars *v, +- struct pipe_ctx *pipe) ++ struct pipe_ctx *pipe, ++ int in_idx) + { + struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); + struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs; +@@ -439,6 +440,21 @@ static void dcn_bw_calc_rq_dlg_ttu( + input.clks_cfg.socclk_mhz = v->socclk; + input.clks_cfg.voltage = v->voltage_level; + // dc->dml.logger = pool->base.logger; ++ input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444; ++ input.dout.output_type = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp; ++ //input[in_idx].dout.output_standard; ++ switch (v->output_deep_color[in_idx]) { ++ case dcn_bw_encoder_12bpc: ++ input.dout.output_bpc = dm_out_12; ++ break; ++ case dcn_bw_encoder_10bpc: ++ input.dout.output_bpc = dm_out_10; ++ break; ++ case dcn_bw_encoder_8bpc: ++ default: ++ input.dout.output_bpc = dm_out_8; ++ break; ++ } + + /*todo: soc->sr_enter_plus_exit_time??*/ + dlg_sys_param.t_srx_delay_us = dc->dcn_ip.dcfclk_cstate_latency / v->dcf_clk_deep_sleep; +@@ -487,6 +503,21 @@ static void dcn_dml_wm_override( + input[in_idx].clks_cfg.refclk_mhz = pool->ref_clock_inKhz / 1000; + input[in_idx].clks_cfg.socclk_mhz = v->socclk; + input[in_idx].clks_cfg.voltage = v->voltage_level; ++ input[in_idx].dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444; ++ input[in_idx].dout.output_type = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp; ++ //input[in_idx].dout.output_standard; ++ switch (v->output_deep_color[in_idx]) { ++ case dcn_bw_encoder_12bpc: ++ input[in_idx].dout.output_bpc = dm_out_12; ++ break; ++ case dcn_bw_encoder_10bpc: ++ input[in_idx].dout.output_bpc = dm_out_10; ++ break; ++ case dcn_bw_encoder_8bpc: ++ default: ++ input[in_idx].dout.output_bpc = dm_out_8; ++ break; ++ } + pipe_ctx_to_e2e_pipe_params(pipe, &input[in_idx].pipe); + dml_rq_dlg_get_rq_reg( + dml, +@@ -1060,7 +1091,7 @@ bool dcn_validate_bandwidth( + pipe, hsplit_pipe); + } + +- dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe); ++ dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx); + } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { + /* merge previously split pipe */ + pipe->bottom_pipe = hsplit_pipe->bottom_pipe; +@@ -1073,7 +1104,7 @@ bool dcn_validate_bandwidth( + resource_build_scaling_params(pipe); + } + /* for now important to do this after pipe split for building e2e params */ +- dcn_bw_calc_rq_dlg_ttu(dc, v, pipe); ++ dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx); + } + + input_idx++; +-- +2.7.4 + |