diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/2892-drm-amdgpu-add-new-member-in-amdgpu_device-for-vmhub.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/2892-drm-amdgpu-add-new-member-in-amdgpu_device-for-vmhub.patch | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/2892-drm-amdgpu-add-new-member-in-amdgpu_device-for-vmhub.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/2892-drm-amdgpu-add-new-member-in-amdgpu_device-for-vmhub.patch new file mode 100644 index 00000000..1484aeb7 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/2892-drm-amdgpu-add-new-member-in-amdgpu_device-for-vmhub.patch @@ -0,0 +1,93 @@ +From 6b8f9c7b687839d49204c4b1aa058b950b25bb45 Mon Sep 17 00:00:00 2001 +From: Le Ma <le.ma@amd.com> +Date: Fri, 31 Aug 2018 14:17:28 +0800 +Subject: [PATCH 2892/2940] drm/amdgpu: add new member in amdgpu_device for + vmhub counts per asic chip + +It aims to replace AMDGPU_MAX_VMHUBS in for loop to initialize registers. + +Signed-off-by: Le Ma <le.ma@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + + drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 + + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 +++++++--- + 3 files changed, 9 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index 6668e8ae4685..717f9eb96bc2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -876,6 +876,7 @@ struct amdgpu_device { + dma_addr_t dummy_page_addr; + struct amdgpu_vm_manager vm_manager; + struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; ++ unsigned num_vmhubs; + + /* memory management */ + struct amdgpu_mman mman; +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +index 8cfc3aa32391..a0bd14e9b8fe 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +@@ -603,6 +603,7 @@ static int gmc_v10_0_sw_init(void *handle) + switch (adev->asic_type) { + case CHIP_NAVI10: + case CHIP_NAVI14: ++ adev->num_vmhubs = 2; + /* + * To fulfill 4-level page support, + * vm size is 256TB (48bit), maximum size of Navi10/Navi14, +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +index a27cfd6d1402..6edd5e579a83 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -280,7 +280,7 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: +- for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) { ++ for (j = 0; j < adev->num_vmhubs; j++) { + hub = &adev->vmhub[j]; + for (i = 0; i < 16; i++) { + reg = hub->vm_context0_cntl + i; +@@ -291,7 +291,7 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, + } + break; + case AMDGPU_IRQ_STATE_ENABLE: +- for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) { ++ for (j = 0; j < adev->num_vmhubs; j++) { + hub = &adev->vmhub[j]; + for (i = 0; i < 16; i++) { + reg = hub->vm_context0_cntl + i; +@@ -415,7 +415,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, + const unsigned eng = 17; + unsigned i, j; + +- for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { ++ for (i = 0; i < adev->num_vmhubs; ++i) { + struct amdgpu_vmhub *hub = &adev->vmhub[i]; + u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type); + +@@ -973,6 +973,8 @@ static int gmc_v9_0_sw_init(void *handle) + adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); + switch (adev->asic_type) { + case CHIP_RAVEN: ++ adev->num_vmhubs = 2; ++ + if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { + amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); + } else { +@@ -985,6 +987,8 @@ static int gmc_v9_0_sw_init(void *handle) + case CHIP_VEGA10: + case CHIP_VEGA12: + case CHIP_VEGA20: ++ adev->num_vmhubs = 2; ++ + /* + * To fulfill 4-level page support, + * vm size is 256TB (48bit), maximum size of Vega10, +-- +2.17.1 + |