diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/2631-drm-amdgpu-sdma5-update-sdma5-golden-settings-for-na.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/2631-drm-amdgpu-sdma5-update-sdma5-golden-settings-for-na.patch | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/2631-drm-amdgpu-sdma5-update-sdma5-golden-settings-for-na.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/2631-drm-amdgpu-sdma5-update-sdma5-golden-settings-for-na.patch new file mode 100644 index 00000000..f9de39db --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/2631-drm-amdgpu-sdma5-update-sdma5-golden-settings-for-na.patch @@ -0,0 +1,40 @@ +From ec41f071019611afc9cba4d7a328cf987f1ed7b0 Mon Sep 17 00:00:00 2001 +From: tiancyin <tianci.yin@amd.com> +Date: Tue, 21 May 2019 14:43:48 +0800 +Subject: [PATCH 2631/2940] drm/amdgpu/sdma5: update sdma5 golden settings for + navi14 + +add new registers: + mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, + mmSDMA1_RLC3_RB_WPTR_POLL_CNTL + +Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> +Signed-off-by: tiancyin <tianci.yin@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +index 9ef36eb3ecfd..dbfb1845297d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +@@ -62,6 +62,7 @@ static const struct soc15_reg_golden golden_settings_sdma_5[] = { + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), +@@ -73,6 +74,7 @@ static const struct soc15_reg_golden golden_settings_sdma_5[] = { + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), +-- +2.17.1 + |