diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/2517-drm-amd-display-Change-DCN2-vupdate-start-programmin.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/2517-drm-amd-display-Change-DCN2-vupdate-start-programmin.patch | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/2517-drm-amd-display-Change-DCN2-vupdate-start-programmin.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/2517-drm-amd-display-Change-DCN2-vupdate-start-programmin.patch new file mode 100644 index 00000000..39b7fa57 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/2517-drm-amd-display-Change-DCN2-vupdate-start-programmin.patch @@ -0,0 +1,47 @@ +From d1774cb477cdf16890f26a34313e979fda14ff4a Mon Sep 17 00:00:00 2001 +From: Eryk Brol <eryk.brol@amd.com> +Date: Mon, 15 Apr 2019 16:09:01 -0400 +Subject: [PATCH 2517/2940] drm/amd/display: Change DCN2 vupdate start + programming + +[Why] +In order to ensure that incoming flips are latched and +complete immediately, we need to program the vupdate +interrupt to come during the back porch of each frame. + +[How] +Program the vupdate start_line to be in the back porch +like it's done for DCN1. + +Signed-off-by: Eryk Brol <eryk.brol@amd.com> +Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 9 +++------ + 1 file changed, 3 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +index e7580e6e0fb6..f9eae47f7be3 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +@@ -1704,13 +1704,10 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, + void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx) + { + struct timing_generator *tg = pipe_ctx->stream_res.tg; +- int start_position = get_vupdate_offset_from_vsync(pipe_ctx); +- uint32_t start_line; ++ int start_line = get_vupdate_offset_from_vsync(pipe_ctx); + +- if (start_position < 0) +- start_line = pipe_ctx->stream->timing.v_total + start_position - 1; +- else +- start_line = start_position; ++ if (start_line < 0) ++ start_line = 0; + + if (tg->funcs->setup_vertical_interrupt2) + tg->funcs->setup_vertical_interrupt2(tg, start_line); +-- +2.17.1 + |