diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/2048-drm-amdgpu-Fixed-missing-to-clear-some-EDC-count.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/2048-drm-amdgpu-Fixed-missing-to-clear-some-EDC-count.patch | 142 |
1 files changed, 142 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/2048-drm-amdgpu-Fixed-missing-to-clear-some-EDC-count.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/2048-drm-amdgpu-Fixed-missing-to-clear-some-EDC-count.patch new file mode 100644 index 00000000..75a4b3e7 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/2048-drm-amdgpu-Fixed-missing-to-clear-some-EDC-count.patch @@ -0,0 +1,142 @@ +From d39f45e2dea34baa1d3112015e7fdecb42c0c1b6 Mon Sep 17 00:00:00 2001 +From: James Zhu <James.Zhu@amd.com> +Date: Tue, 4 Jun 2019 12:49:02 -0400 +Subject: [PATCH 2048/2940] drm/amdgpu: Fixed missing to clear some EDC count + +EDC counts are related to instance and se. They are not the same +for different type of EDC. EDC clearing are changed to base on +individual EDC's instance and SE number. + +Signed-off-by: James Zhu <James.Zhu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 85 +++++++++++++-------------- + drivers/gpu/drm/amd/amdgpu/soc15.h | 2 + + 2 files changed, 42 insertions(+), 45 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 879b496ebde8..0377bb021a43 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -3590,37 +3590,38 @@ static const struct soc15_reg_entry sgpr_init_regs[] = { + }; + + static const struct soc15_reg_entry sec_ded_counter_registers[] = { +- { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED) }, +- { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO) }, +- { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2) }, +- { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2) }, +- { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT) }, +- { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2) }, +- { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT) }, ++ { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1}, ++ { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1}, ++ { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1}, ++ { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1}, ++ { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1}, ++ { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1}, ++ { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1}, ++ { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1}, ++ { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1}, ++ { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1}, ++ { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1}, ++ { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1}, ++ { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1}, ++ { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6}, ++ { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16}, ++ { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16}, ++ { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16}, ++ { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16}, ++ { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16}, ++ { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16}, ++ { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16}, ++ { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6}, ++ { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16}, ++ { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16}, ++ { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1}, ++ { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1}, ++ { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32}, ++ { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32}, ++ { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72}, ++ { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16}, ++ { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2}, ++ { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6}, + }; + + static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) +@@ -3628,7 +3629,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) + struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; + struct amdgpu_ib ib; + struct dma_fence *f = NULL; +- int r, i, j; ++ int r, i, j, k; + unsigned total_size, vgpr_offset, sgpr_offset; + u64 gpu_addr; + +@@ -3740,19 +3741,13 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) + + /* read back registers to clear the counters */ + mutex_lock(&adev->grbm_idx_mutex); +- for (j = 0; j < 16; j++) { +- gfx_v9_0_select_se_sh(adev, 0x01, 0x0, j); +- for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) +- RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i])); +- gfx_v9_0_select_se_sh(adev, 0x02, 0x0, j); +- for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) +- RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i])); +- gfx_v9_0_select_se_sh(adev, 0x03, 0x0, j); +- for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) +- RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i])); +- gfx_v9_0_select_se_sh(adev, 0x04, 0x0, j); +- for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) +- RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i])); ++ for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) { ++ for (j = 0; j < sec_ded_counter_registers[i].se_num; j++) { ++ for (k = 0; k < sec_ded_counter_registers[i].instance; k++) { ++ gfx_v9_0_select_se_sh(adev, j, 0x0, k); ++ RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i])); ++ } ++ } + } + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); + mutex_unlock(&adev->grbm_idx_mutex); +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h +index 06f39f5bbf76..48e824d52ad9 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.h ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.h +@@ -48,6 +48,8 @@ struct soc15_reg_entry { + uint32_t seg; + uint32_t reg_offset; + uint32_t reg_value; ++ uint32_t se_num; ++ uint32_t instance; + }; + + #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg +-- +2.17.1 + |