diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0392-drm-amdgpu-powerplay-add-smu-smc_table_manager-callb.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0392-drm-amdgpu-powerplay-add-smu-smc_table_manager-callb.patch | 112 |
1 files changed, 112 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0392-drm-amdgpu-powerplay-add-smu-smc_table_manager-callb.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0392-drm-amdgpu-powerplay-add-smu-smc_table_manager-callb.patch new file mode 100644 index 00000000..7d0377a5 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0392-drm-amdgpu-powerplay-add-smu-smc_table_manager-callb.patch @@ -0,0 +1,112 @@ +From 80aac4dbaae7e83a51df31651692419f528fee18 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 20 Sep 2018 21:15:39 -0500 +Subject: [PATCH 0392/2940] drm/amdgpu/powerplay: add smu smc_table_manager + callback for vega12 + +For consistency with other asics. + +Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 8 +++---- + .../drm/amd/powerplay/smumgr/vega12_smumgr.c | 22 +++++++++++++++---- + .../drm/amd/powerplay/smumgr/vega12_smumgr.h | 4 ---- + 3 files changed, 22 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c +index 0789d64246ca..de81abfbf4f1 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c +@@ -745,8 +745,8 @@ static int vega12_init_smc_table(struct pp_hwmgr *hwmgr) + + memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t)); + +- result = vega12_copy_table_to_smc(hwmgr, +- (uint8_t *)pp_table, TABLE_PPTABLE); ++ result = smum_smc_table_manager(hwmgr, ++ (uint8_t *)pp_table, TABLE_PPTABLE, false); + PP_ASSERT_WITH_CODE(!result, + "Failed to upload PPtable!", return result); + +@@ -2103,8 +2103,8 @@ static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr) + + if ((data->water_marks_bitmap & WaterMarksExist) && + !(data->water_marks_bitmap & WaterMarksLoaded)) { +- result = vega12_copy_table_to_smc(hwmgr, +- (uint8_t *)wm_table, TABLE_WATERMARKS); ++ result = smum_smc_table_manager(hwmgr, ++ (uint8_t *)wm_table, TABLE_WATERMARKS, false); + PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL); + data->water_marks_bitmap |= WaterMarksLoaded; + } +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c +index 7f0e2109f40d..ddb801517667 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c +@@ -37,8 +37,8 @@ + * @param hwmgr the address of the HW manager + * @param table_id the driver's table ID to copy from + */ +-int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr, +- uint8_t *table, int16_t table_id) ++static int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr, ++ uint8_t *table, int16_t table_id) + { + struct vega12_smumgr *priv = + (struct vega12_smumgr *)(hwmgr->smu_backend); +@@ -75,8 +75,8 @@ int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr, + * @param hwmgr the address of the HW manager + * @param table_id the table to copy from + */ +-int vega12_copy_table_to_smc(struct pp_hwmgr *hwmgr, +- uint8_t *table, int16_t table_id) ++static int vega12_copy_table_to_smc(struct pp_hwmgr *hwmgr, ++ uint8_t *table, int16_t table_id) + { + struct vega12_smumgr *priv = + (struct vega12_smumgr *)(hwmgr->smu_backend); +@@ -351,6 +351,19 @@ static int vega12_start_smu(struct pp_hwmgr *hwmgr) + return 0; + } + ++static int vega12_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, ++ uint16_t table_id, bool rw) ++{ ++ int ret; ++ ++ if (rw) ++ ret = vega12_copy_table_from_smc(hwmgr, table, table_id); ++ else ++ ret = vega12_copy_table_to_smc(hwmgr, table, table_id); ++ ++ return ret; ++} ++ + const struct pp_smumgr_func vega12_smu_funcs = { + .smu_init = &vega12_smu_init, + .smu_fini = &vega12_smu_fini, +@@ -362,4 +375,5 @@ const struct pp_smumgr_func vega12_smu_funcs = { + .upload_pptable_settings = NULL, + .is_dpm_running = vega12_is_dpm_running, + .get_argument = smu9_get_argument, ++ .smc_table_manager = vega12_smc_table_manager, + }; +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h +index b285cbc04019..aeec965ce81f 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h +@@ -48,10 +48,6 @@ struct vega12_smumgr { + #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000 + #define SMU_FEATURES_HIGH_SHIFT 32 + +-int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr, +- uint8_t *table, int16_t table_id); +-int vega12_copy_table_to_smc(struct pp_hwmgr *hwmgr, +- uint8_t *table, int16_t table_id); + int vega12_enable_smc_features(struct pp_hwmgr *hwmgr, + bool enable, uint64_t feature_mask); + int vega12_get_enabled_smc_features(struct pp_hwmgr *hwmgr, +-- +2.17.1 + |