diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0142-drm-amdgpu-hybrid-add-query-amdgpu-capability-functi.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0142-drm-amdgpu-hybrid-add-query-amdgpu-capability-functi.patch | 103 |
1 files changed, 103 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0142-drm-amdgpu-hybrid-add-query-amdgpu-capability-functi.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0142-drm-amdgpu-hybrid-add-query-amdgpu-capability-functi.patch new file mode 100644 index 00000000..a065c200 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0142-drm-amdgpu-hybrid-add-query-amdgpu-capability-functi.patch @@ -0,0 +1,103 @@ +From 22eb31843de082d9b12495d99e2859bb4781592f Mon Sep 17 00:00:00 2001 +From: jimqu <Jim.Qu@amd.com> +Date: Mon, 16 Nov 2015 14:03:15 +0800 +Subject: [PATCH 0142/2940] drm/amdgpu: [hybrid] add query amdgpu capability + function + +with this function, it could return capability to user space driver. + +Change-Id: Icad47e8d0621f9e8b8b9baedb751c11ded6c9449 +Signed-off-by: JimQu <Jim.Qu@amd.com> +Reviewed-by: Chunming Zhou <david1.zhou@amd.com> +Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> + + Conflicts: + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +++ + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 9 +++++++++ + include/uapi/drm/amdgpu_drm.h | 6 ++++++ + 4 files changed, 19 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index 6730ec4e58d0..4ebb6ea00bc5 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -114,6 +114,7 @@ extern int amdgpu_vm_update_mode; + extern int amdgpu_dc; + extern int amdgpu_sched_jobs; + extern int amdgpu_sched_hw_submission; ++extern int amdgpu_no_evict; + extern uint amdgpu_pcie_gen_cap; + extern uint amdgpu_pcie_lane_cap; + extern uint amdgpu_cg_mask; +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +index 0ec1c5cfdb71..e72c0f80adb7 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +@@ -107,6 +107,7 @@ int amdgpu_exp_hw_support = 0; + int amdgpu_dc = -1; + int amdgpu_sched_jobs = 32; + int amdgpu_sched_hw_submission = 2; ++int amdgpu_no_evict = 0; + uint amdgpu_pcie_gen_cap = 0; + uint amdgpu_pcie_lane_cap = 0; + uint amdgpu_cg_mask = 0xffffffff; +@@ -361,6 +362,8 @@ module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); + MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); + module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); + ++MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); ++module_param_named(no_evict, amdgpu_no_evict, int, 0444); + /** + * DOC: pcie_gen_cap (uint) + * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +index b5eaf39cd301..dacc9b7c2526 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +@@ -749,6 +749,15 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file + return -EINVAL; + } + } ++ case AMDGPU_INFO_CAPABILITY: { ++ struct drm_amdgpu_capability cap; ++ ++ memset(&cap, 0, sizeof(cap)); ++ if (amdgpu_no_evict) ++ cap.flag |= AMDGPU_CAPABILITY_PIN_MEM_FLAG; ++ return copy_to_user(out, &cap, ++ min((size_t)size, sizeof(cap))) ? -EFAULT : 0; ++ } + case AMDGPU_INFO_SENSOR: { + if (!adev->pm.dpm_enabled) + return -ENOENT; +diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h +index 0652038bd75d..a2829eb514c3 100644 +--- a/include/uapi/drm/amdgpu_drm.h ++++ b/include/uapi/drm/amdgpu_drm.h +@@ -731,6 +731,8 @@ struct drm_amdgpu_cs_chunk_data { + #define AMDGPU_INFO_CAPABILITY 0x50 + /* virtual range */ + #define AMDGPU_INFO_VIRTUAL_RANGE 0x51 ++/* query pin memory capability */ ++#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) + + #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 + #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff +@@ -1017,6 +1019,10 @@ struct drm_amdgpu_virtual_range { + uint64_t end; + }; + ++struct drm_amdgpu_capability { ++ __u32 flag; ++}; ++ + /* + * Definition of free sync enter and exit signals + * We may have more options in the future +-- +2.17.1 + |