diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/3586-drm-amdgpu-powerplay-smu7-drop-refresh-rate-checks-f.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/3586-drm-amdgpu-powerplay-smu7-drop-refresh-rate-checks-f.patch | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/3586-drm-amdgpu-powerplay-smu7-drop-refresh-rate-checks-f.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/3586-drm-amdgpu-powerplay-smu7-drop-refresh-rate-checks-f.patch new file mode 100644 index 00000000..0036fa41 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/3586-drm-amdgpu-powerplay-smu7-drop-refresh-rate-checks-f.patch @@ -0,0 +1,33 @@ +From 6210dcf5a34980b28d50d90c37efd73591fb6451 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Tue, 13 Feb 2018 14:37:36 -0500 +Subject: [PATCH 3586/4131] drm/amdgpu/powerplay/smu7: drop refresh rate checks + for mclk switching + +The logic has moved to cgs. mclk switching with DC at higher refresh +rates should work. + +Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Cc: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +index 17bf60e..31cf629 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +@@ -2908,8 +2908,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + else + disable_mclk_switching = ((1 < info.display_count) || + disable_mclk_switching_for_frame_lock || +- smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) || +- (mode_info.refresh_rate > 120)); ++ smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us)); + + sclk = smu7_ps->performance_levels[0].engine_clock; + mclk = smu7_ps->performance_levels[0].memory_clock; +-- +2.7.4 + |