diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0917-drm-amdgpu-dce11-update-pll-programming-for-ELM-BAF.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0917-drm-amdgpu-dce11-update-pll-programming-for-ELM-BAF.patch | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0917-drm-amdgpu-dce11-update-pll-programming-for-ELM-BAF.patch b/common/recipes-kernel/linux/files/0917-drm-amdgpu-dce11-update-pll-programming-for-ELM-BAF.patch new file mode 100644 index 00000000..a1d1b7a2 --- /dev/null +++ b/common/recipes-kernel/linux/files/0917-drm-amdgpu-dce11-update-pll-programming-for-ELM-BAF.patch @@ -0,0 +1,76 @@ +From 7671e6b69ffaffe933791336c4924f9a55b8a9de Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 15 Oct 2015 16:35:33 -0400 +Subject: [PATCH 0917/1110] drm/amdgpu/dce11: update pll programming for + ELM/BAF +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +SetPixelClock table handles pll divider calculation and +spread spectrum setup, so no need to use calculate the +dividers and call the ss enable cmd table. + +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 31 +++++++++++++++++++++++++++++-- + 1 file changed, 29 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +index 92a242a..d068de8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +@@ -2751,7 +2751,17 @@ static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) + case ATOM_PPLL2: + /* disable the ppll */ + amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, +- 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); ++ 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); ++ break; ++ case ATOM_COMBOPHY_PLL0: ++ case ATOM_COMBOPHY_PLL1: ++ case ATOM_COMBOPHY_PLL2: ++ case ATOM_COMBOPHY_PLL3: ++ case ATOM_COMBOPHY_PLL4: ++ case ATOM_COMBOPHY_PLL5: ++ /* disable the ppll */ ++ amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id, ++ 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); + break; + default: + break; +@@ -2769,11 +2779,28 @@ static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, + int x, int y, struct drm_framebuffer *old_fb) + { + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); ++ struct drm_device *dev = crtc->dev; ++ struct amdgpu_device *adev = dev->dev_private; + + if (!amdgpu_crtc->adjusted_clock) + return -EINVAL; + +- amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); ++ if ((adev->asic_type == CHIP_ELLESMERE) || ++ (adev->asic_type == CHIP_BAFFIN)) { ++ struct amdgpu_encoder *amdgpu_encoder = ++ to_amdgpu_encoder(amdgpu_crtc->encoder); ++ int encoder_mode = ++ amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); ++ ++ /* SetPixelClock calculates the plls and ss values now */ ++ amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, ++ amdgpu_crtc->pll_id, ++ encoder_mode, amdgpu_encoder->encoder_id, ++ adjusted_mode->clock, 0, 0, 0, 0, ++ amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); ++ } else { ++ amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); ++ } + amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); + dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); + amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); +-- +2.7.4 + |