diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0886-drm-amd-dal-Fix-compile-error-for-case-CONFIG_DRM_AM.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0886-drm-amd-dal-Fix-compile-error-for-case-CONFIG_DRM_AM.patch | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0886-drm-amd-dal-Fix-compile-error-for-case-CONFIG_DRM_AM.patch b/common/recipes-kernel/linux/files/0886-drm-amd-dal-Fix-compile-error-for-case-CONFIG_DRM_AM.patch new file mode 100644 index 00000000..c06d6d75 --- /dev/null +++ b/common/recipes-kernel/linux/files/0886-drm-amd-dal-Fix-compile-error-for-case-CONFIG_DRM_AM.patch @@ -0,0 +1,62 @@ +From 5c53f33340ccb41596cb83e2e4a7384ced6449c0 Mon Sep 17 00:00:00 2001 +From: David Rokhvarg <David.Rokhvarg@amd.com> +Date: Mon, 7 Dec 2015 13:29:36 -0500 +Subject: [PATCH 0886/1050] drm/amd/dal: Fix compile error for case + "CONFIG_DRM_AMD_POWERPLAY not defined". + +Change-Id: Ib0f2233faa6f7073f030f664936562aeb51fa134 +Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com> +Signed-off-by: Harry Wentland <harry.wentland@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c | 11 +++++------ + 1 file changed, 5 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c +index 2c02d18..e9308f3 100644 +--- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c ++++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c +@@ -234,7 +234,6 @@ bool dc_service_pp_get_clock_levels_by_type( + enum dc_pp_clock_type clk_type, + struct dc_pp_clock_levels *clks) + { +- + /* + #ifdef CONFIG_DRM_AMD_POWERPLAY + if(amd_powerplay_get_clocks_by_type(adev->powerplay.pp_handle, +@@ -243,17 +242,12 @@ bool dc_service_pp_get_clock_levels_by_type( + divide by 10 & push to the clks which kHz + #endif + */ +- +- struct amdgpu_device *adev = ctx->driver_context; +- + uint32_t disp_clks_in_khz[8] = { + 300000, 411430, 480000, 533340, 626090, 626090, 626090, 626090 }; + uint32_t sclks_in_khz[8] = { + 200000, 266670, 342860, 411430, 450000, 514290, 576000, 626090 }; + uint32_t mclks_in_khz[8] = { 333000, 800000 }; + +- struct amd_pp_dal_clock_info info = {0}; +- + switch (clk_type) { + case DC_PP_CLOCK_TYPE_DISPLAY_CLK: + clks->num_levels = 8; +@@ -273,9 +267,14 @@ bool dc_service_pp_get_clock_levels_by_type( + default: + return false; + } ++ + #ifdef CONFIG_DRM_AMD_POWERPLAY + if (clk_type == DC_PP_CLOCK_TYPE_ENGINE_CLK || + clk_type == DC_PP_CLOCK_TYPE_DISPLAY_CLK) { ++ ++ struct amdgpu_device *adev = ctx->driver_context; ++ struct amd_pp_dal_clock_info info = {0}; ++ + if (0 == amd_powerplay_get_display_power_level( + adev->powerplay.pp_handle, &info) && + info.level < clks->num_levels) { +-- +1.9.1 + |