diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0877-drm-amd-dal-Modified-service-interface-for-pplib.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0877-drm-amd-dal-Modified-service-interface-for-pplib.patch | 231 |
1 files changed, 231 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0877-drm-amd-dal-Modified-service-interface-for-pplib.patch b/common/recipes-kernel/linux/files/0877-drm-amd-dal-Modified-service-interface-for-pplib.patch new file mode 100644 index 00000000..c955141f --- /dev/null +++ b/common/recipes-kernel/linux/files/0877-drm-amd-dal-Modified-service-interface-for-pplib.patch @@ -0,0 +1,231 @@ +From 574378c03ed067db2260a87b4a31b223b6e974e8 Mon Sep 17 00:00:00 2001 +From: Yongqiang Sun <yongqiang.sun@amd.com> +Date: Tue, 1 Dec 2015 09:19:28 -0500 +Subject: [PATCH 0877/1050] drm/amd/dal: Modified service interface for pplib. + +Change-Id: Ic386876cf18b303de4ffa5008bd96af6061fdd54 +Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> +Signed-off-by: Harry Wentland <harry.wentland@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + .../drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c | 55 ++++++++++------ + drivers/gpu/drm/amd/dal/dc/core/dc.c | 2 +- + drivers/gpu/drm/amd/dal/dc/dc_services.h | 75 ++++++++++++---------- + 3 files changed, 76 insertions(+), 56 deletions(-) + +diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c +index 3b97b64..b2886d2 100644 +--- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c ++++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c +@@ -29,7 +29,6 @@ + #include <drm/drmP.h> + #include <drm/drm_crtc_helper.h> + #include <drm/amdgpu_drm.h> +- + #include "amdgpu.h" + #include "dal_services.h" + #include "amdgpu_dm.h" +@@ -158,7 +157,7 @@ bool dc_service_pp_pre_dce_clock_change( + return false; + } + +-bool dc_service_pp_post_dce_clock_change( ++bool dc_service_pp_apply_display_requirements( + struct dc_context *ctx, + const struct dc_pp_display_configuration *pp_display_cfg) + { +@@ -194,6 +193,7 @@ bool dc_service_pp_post_dce_clock_change( + /* TODO: replace by a separate call to 'apply display cfg'? */ + amdgpu_pm_compute_clocks(adev); + } ++ + return true; + #else + return false; +@@ -229,31 +229,46 @@ bool dc_service_get_system_clocks_range( + } + + +-bool dc_service_get_clock_levels_by_type( ++bool dc_service_pp_get_clock_levels_by_type( + struct dc_context *ctx, + enum dc_pp_clock_type clk_type, +- struct dc_pp_clock_levels *clk_level_info) ++ struct dc_pp_clock_levels *clks) + { +- /* TODO: follow implementation of: +- * PhwCz_GetClocksByType - powerplay\hwmgr\cz_hwmgr.c +- * PHM_GetClockByType - powerplay\hwmgr\hardwaremanager.c +- * PP_IRI_GetClockByType - powerplay\eventmgr\iri.c */ +- +- DRM_INFO("%s - not implemented\n", __func__); +- return false; +-} ++#ifdef CONFIG_DRM_AMD_POWERPLAY ++/* TODO: get clks from pplib. ++ struct amdgpu_device *adev = ctx->driver_context; + +-bool dc_service_get_static_clocks( +- struct dc_context *ctx, +- struct dc_pp_static_clock_info *static_clk_info) +-{ +- /* TODO: follow implementation of: +- * PhwCz_GetDALPowerLevel - powerplay\hwmgr\cz_hwmgr.c +- * PHM_GetDALPowerLevel - powerplay\hwmgr\hardwaremanager.c +- * PP_IRI_GetStaticClocksInfo - powerplay\eventmgr\iri.c */ ++ return (amd_powerplay_get_clocks_by_type(adev->powerplay.pp_handle, ++ (int)clk_type, (void *)clks) == 0); ++ */ ++ uint32_t disp_clks_in_hz[8] = { ++ 30000, 41143, 48000, 53334, 62609, 62609, 62609, 62609 }; ++ uint32_t sclks_in_hz[8] = { ++ 20000, 26667, 34286, 41143, 45000, 51429, 57600, 62609 }; ++ uint32_t mclks_in_hz[8] = { 33300, 80000, 0, 0, 0, 0, 0, 0 }; ++ ++ switch (clk_type) { ++ case DC_PP_CLOCK_TYPE_DISPLAY_CLK: ++ clks->num_levels = 8; ++ dc_service_memmove(clks->clocks_in_hz, disp_clks_in_hz, 8); ++ break; ++ case DC_PP_CLOCK_TYPE_ENGINE_CLK: ++ clks->num_levels = 8; ++ dc_service_memmove(clks->clocks_in_hz, sclks_in_hz, 8); ++ break; ++ case DC_PP_CLOCK_TYPE_MEMORY_CLK: ++ clks->num_levels = 2; ++ dc_service_memmove(clks->clocks_in_hz, mclks_in_hz, 8); ++ break; ++ default: ++ return false; ++ } + ++ return true; ++#else + DRM_INFO("%s - not implemented\n", __func__); + return false; ++#endif + } + + /**** end of power component interfaces ****/ +diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c +index 1eee73e..0b7c252 100644 +--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c +@@ -528,7 +528,7 @@ static void pplib_post_set_mode( + pp_display_cfg.crtc_index = 0; + pp_display_cfg.line_time_in_us = 0; + +- dc_service_pp_post_dce_clock_change(dc->ctx, &pp_display_cfg); ++ dc_service_pp_apply_display_requirements(dc->ctx, &pp_display_cfg); + } + + bool dc_commit_targets( +diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services.h b/drivers/gpu/drm/amd/dal/dc/dc_services.h +index 314ae58..42febce 100644 +--- a/drivers/gpu/drm/amd/dal/dc/dc_services.h ++++ b/drivers/gpu/drm/amd/dal/dc/dc_services.h +@@ -115,20 +115,6 @@ struct dc_pp_display_configuration { + uint32_t line_time_in_us; + }; + +-enum dc_pp_clock_type { +- DC_PP_CLOCK_TYPE_DISPLAY_CLK = 1, +- DC_PP_CLOCK_TYPE_ENGINE_CLK, +- DC_PP_CLOCK_TYPE_MEMORY_CLK +-}; +- +-#define DC_PP_MAX_CLOCK_LEVELS 8 +- +-struct dc_pp_clock_levels { +- enum dc_pp_clock_type clock_type; +- uint32_t num_levels; +- uint32_t clocks_in_hz[DC_PP_MAX_CLOCK_LEVELS]; +-}; +- + enum dc_pp_clocks_state { + DC_PP_CLOCKS_STATE_INVALID = 0, + DC_PP_CLOCKS_STATE_ULTRA_LOW, +@@ -156,21 +142,6 @@ struct dc_pp_static_clock_info { + enum dc_pp_clocks_state max_clocks_state; + }; + +-/* DAL calls this function to notify PP about completion of Mode Set. +- * For PP it means that current DCE clocks are those which were returned +- * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter. +- * +- * If the clocks are higher than before, then PP does nothing. +- * +- * If the clocks are lower than before, then PP reduces the voltage. +- * +- * \returns true - call is successful +- * false - call failed +- */ +-bool dc_service_pp_post_dce_clock_change( +- struct dc_context *ctx, +- const struct dc_pp_display_configuration *pp_display_cfg); +- + /* The returned clocks range are 'static' system clocks which will be used for + * mode validation purposes. + * +@@ -181,18 +152,52 @@ bool dc_service_get_system_clocks_range( + struct dc_context *ctx, + struct dal_system_clock_range *sys_clks); + ++enum dc_pp_clock_type { ++ DC_PP_CLOCK_TYPE_DISPLAY_CLK = 1, ++ DC_PP_CLOCK_TYPE_ENGINE_CLK, ++ DC_PP_CLOCK_TYPE_MEMORY_CLK ++}; ++ ++#define DC_PP_MAX_CLOCK_LEVELS 8 ++ ++struct dc_pp_clock_levels { ++ uint32_t num_levels; ++ uint32_t clocks_in_hz[DC_PP_MAX_CLOCK_LEVELS]; ++ ++ /* TODO: add latency for baffin ++ * do we need to know invalid (unsustainable boost) level for watermark ++ * programming? if not we can just report less elements in array ++ */ ++}; + +-bool dc_service_get_clock_levels_by_type( ++/* Gets valid clocks levels from pplib ++ * ++ * input: clk_type - display clk / sclk / mem clk ++ * ++ * output: array of valid clock levels for given type in ascending order, ++ * with invalid levels filtered out ++ * ++ */ ++bool dc_service_pp_get_clock_levels_by_type( + struct dc_context *ctx, + enum dc_pp_clock_type clk_type, + struct dc_pp_clock_levels *clk_level_info); + +-/* Use this for mode validation. +- * TODO: when this interface is implemented on Linux, should we remove +- * dc_service_get_system_clocks_range() ?? */ +-bool dc_service_get_static_clocks( ++ ++/* DAL calls this function to notify PP about completion of Mode Set. ++ * For PP it means that current DCE clocks are those which were returned ++ * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter. ++ * ++ * If the clocks are higher than before, then PP does nothing. ++ * ++ * If the clocks are lower than before, then PP reduces the voltage. ++ * ++ * \returns true - call is successful ++ * false - call failed ++ */ ++bool dc_service_pp_apply_display_requirements( + struct dc_context *ctx, +- struct dc_pp_static_clock_info *static_clk_info); ++ const struct dc_pp_display_configuration *pp_display_cfg); + + + /****** end of PP interfaces ******/ +-- +1.9.1 + |