diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0528-drm-amdgpu-fix-typo-in-dce11-watermark-setup.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0528-drm-amdgpu-fix-typo-in-dce11-watermark-setup.patch | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0528-drm-amdgpu-fix-typo-in-dce11-watermark-setup.patch b/common/recipes-kernel/linux/files/0528-drm-amdgpu-fix-typo-in-dce11-watermark-setup.patch new file mode 100644 index 00000000..85a8479b --- /dev/null +++ b/common/recipes-kernel/linux/files/0528-drm-amdgpu-fix-typo-in-dce11-watermark-setup.patch @@ -0,0 +1,31 @@ +From 99a092383794e07d60644b449a01656da112eb1f Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 3 Sep 2015 10:16:23 -0400 +Subject: [PATCH 0528/1050] drm/amdgpu: fix typo in dce11 watermark setup + +Using the wrong watermwark value for the secondary +watermark. Copy paste typo. Noticed by Mykola. + +Reviewed-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Cc: stable@vger.kernel.org +--- + drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +index 70eee80..6411e82 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +@@ -1329,7 +1329,7 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev, + tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); + WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); + tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); +- tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); ++ tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); + tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); + WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); + /* restore original selection */ +-- +1.9.1 + |