diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0324-drm-amdgpu-cz-implement-voltage-validation-properly.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0324-drm-amdgpu-cz-implement-voltage-validation-properly.patch | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0324-drm-amdgpu-cz-implement-voltage-validation-properly.patch b/common/recipes-kernel/linux/files/0324-drm-amdgpu-cz-implement-voltage-validation-properly.patch new file mode 100644 index 00000000..105415f6 --- /dev/null +++ b/common/recipes-kernel/linux/files/0324-drm-amdgpu-cz-implement-voltage-validation-properly.patch @@ -0,0 +1,64 @@ +From f2d52cd4db08db06200176cfebead9778878d4fc Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Tue, 14 Jul 2015 16:16:29 -0400 +Subject: [PATCH 0324/1050] drm/amdgpu/cz: implement voltage validation + properly + +CZ uses a different set of registers compared to previous asics +and supports separate NB and GFX planes. + +Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 23 ++++++++++++++++------- + 1 file changed, 16 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +index 1a2d419..1316d54 100644 +--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c ++++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +@@ -494,6 +494,13 @@ static void cz_dpm_fini(struct amdgpu_device *adev) + amdgpu_free_extended_power_table(adev); + } + ++#define ixSMUSVI_NB_CURRENTVID 0xD8230044 ++#define CURRENT_NB_VID_MASK 0xff000000 ++#define CURRENT_NB_VID__SHIFT 24 ++#define ixSMUSVI_GFX_CURRENTVID 0xD8230048 ++#define CURRENT_GFX_VID_MASK 0xff000000 ++#define CURRENT_GFX_VID__SHIFT 24 ++ + static void + cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, + struct seq_file *m) +@@ -505,18 +512,20 @@ cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, + TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >> + TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT; + u32 sclk, tmp; +- u16 vddc; ++ u16 vddnb, vddgfx; + + if (current_index >= NUM_SCLK_LEVELS) { + seq_printf(m, "invalid dpm profile %d\n", current_index); + } else { + sclk = table->entries[current_index].clk; +- tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) & +- SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> +- SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT; +- vddc = cz_convert_8bit_index_to_voltage(adev, (u16)tmp); +- seq_printf(m, "power level %d sclk: %u vddc: %u\n", +- current_index, sclk, vddc); ++ tmp = (RREG32_SMC(ixSMUSVI_NB_CURRENTVID) & ++ CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT; ++ vddnb = cz_convert_8bit_index_to_voltage(adev, (u16)tmp); ++ tmp = (RREG32_SMC(ixSMUSVI_GFX_CURRENTVID) & ++ CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT; ++ vddgfx = cz_convert_8bit_index_to_voltage(adev, (u16)tmp); ++ seq_printf(m, "power level %d sclk: %u vddnb: %u vddgfx: %u\n", ++ current_index, sclk, vddnb, vddgfx); + } + } + +-- +1.9.1 + |