diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0089-drm-amd-powerplay-fix-boolreturn.cocci-warnings.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0089-drm-amd-powerplay-fix-boolreturn.cocci-warnings.patch | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0089-drm-amd-powerplay-fix-boolreturn.cocci-warnings.patch b/common/recipes-kernel/linux/files/0089-drm-amd-powerplay-fix-boolreturn.cocci-warnings.patch new file mode 100644 index 00000000..073ce483 --- /dev/null +++ b/common/recipes-kernel/linux/files/0089-drm-amd-powerplay-fix-boolreturn.cocci-warnings.patch @@ -0,0 +1,48 @@ +From dca6548892286633a1e156079f1043a620ab0ce9 Mon Sep 17 00:00:00 2001 +From: kbuild test robot <fengguang.wu@intel.com> +Date: Thu, 12 Nov 2015 12:58:34 -0500 +Subject: [PATCH 0089/1110] drm/amd/powerplay: fix boolreturn.cocci warnings + +drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/tonga_hwmgr.c:2653:9-10: WARNING: return of 0/1 in function 'is_pcie_gen2_supported' with return type bool +drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/tonga_hwmgr.c:2645:9-10: WARNING: return of 0/1 in function 'is_pcie_gen3_supported' with return type bool + + Return statements in functions returning bool should use + true/false instead of 1/0. +Generated by: scripts/coccinelle/misc/boolreturn.cocci + +CC: yanyang1 <young.yang@amd.com> +Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/include/amd_pcie_helpers.h | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/include/amd_pcie_helpers.h b/drivers/gpu/drm/amd/include/amd_pcie_helpers.h +index 2cfdf05..5725bf8 100644 +--- a/drivers/gpu/drm/amd/include/amd_pcie_helpers.h ++++ b/drivers/gpu/drm/amd/include/amd_pcie_helpers.h +@@ -28,17 +28,17 @@ + static inline bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap) + { + if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) +- return 1; ++ return true; + +- return 0; ++ return false; + } + + static inline bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap) + { + if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) +- return 1; ++ return true; + +- return 0; ++ return false; + } + + /* Get the new PCIE speed given the ASIC PCIE Cap and the NewState's requested PCIE speed*/ +-- +2.7.4 + |