diff options
Diffstat (limited to 'common/recipes-graphics/drm/libdrm-2.4.66/0021-vc4-Add-headers-and-.pc-files-for-VC4-userspace-deve.patch')
| -rw-r--r-- | common/recipes-graphics/drm/libdrm-2.4.66/0021-vc4-Add-headers-and-.pc-files-for-VC4-userspace-deve.patch | 870 |
1 files changed, 870 insertions, 0 deletions
diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0021-vc4-Add-headers-and-.pc-files-for-VC4-userspace-deve.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0021-vc4-Add-headers-and-.pc-files-for-VC4-userspace-deve.patch new file mode 100644 index 00000000..3b6181fe --- /dev/null +++ b/common/recipes-graphics/drm/libdrm-2.4.66/0021-vc4-Add-headers-and-.pc-files-for-VC4-userspace-deve.patch @@ -0,0 +1,870 @@ +From 3c717f61f885240980bfc4273dbd1fc837edc391 Mon Sep 17 00:00:00 2001 +From: Eric Anholt <eric@anholt.net> +Date: Mon, 25 Jan 2016 10:16:56 -0800 +Subject: [PATCH 021/117] vc4: Add headers and .pc files for VC4 userspace + development. + +The headers were originally written in Mesa, imported to the kernel, +and improved upon in vc4-gpu-tools. These come from the v-g-t copies +and will replace the Mesa and v-g-t copies, and hopefully be used from +new tests in igt, as well. + +v2: Fix linking against libdrm_intel instead of libdrm. +v3: Drop Libs and Cflags since they'll be inherited from libdrm. +v4: Switch to Requires.private. I was wrong about standard practice, + apparently only Intel was doing plain Requires (sorry to all + involved). + +Signed-off-by: Eric Anholt <eric@anholt.net> +--- + Makefile.am | 6 + + configure.ac | 19 +++ + vc4/Makefile.am | 34 +++++ + vc4/Makefile.sources | 3 + + vc4/libdrm_vc4.pc.in | 9 ++ + vc4/vc4_packet.h | 397 ++++++++++++++++++++++++++++++++++++++++++++++++++ + vc4/vc4_qpu_defines.h | 274 ++++++++++++++++++++++++++++++++++ + 7 files changed, 742 insertions(+) + create mode 100644 vc4/Makefile.am + create mode 100644 vc4/Makefile.sources + create mode 100644 vc4/libdrm_vc4.pc.in + create mode 100644 vc4/vc4_packet.h + create mode 100644 vc4/vc4_qpu_defines.h + +diff --git a/Makefile.am b/Makefile.am +index ca41508..feecba7 100644 +--- a/Makefile.am ++++ b/Makefile.am +@@ -29,6 +29,7 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \ + --enable-radeon \ + --enable-amdgpu \ + --enable-nouveau \ ++ --enable-vc4 \ + --enable-vmwgfx \ + --enable-omap-experimental-api \ + --enable-exynos-experimental-api \ +@@ -79,6 +80,10 @@ if HAVE_TEGRA + TEGRA_SUBDIR = tegra + endif + ++if HAVE_VC4 ++VC4_SUBDIR = vc4 ++endif ++ + if BUILD_MANPAGES + if HAVE_MANPAGES_STYLESHEET + MAN_SUBDIR = man +@@ -96,6 +101,7 @@ SUBDIRS = \ + $(EXYNOS_SUBDIR) \ + $(FREEDRENO_SUBDIR) \ + $(TEGRA_SUBDIR) \ ++ $(VC4_SUBDIR) \ + tests \ + $(MAN_SUBDIR) + +diff --git a/configure.ac b/configure.ac +index 4635d18..4eeebfb 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -126,6 +126,11 @@ AC_ARG_ENABLE(tegra-experimental-api, + [Enable support for Tegra's experimental API (default: disabled)]), + [TEGRA=$enableval], [TEGRA=no]) + ++AC_ARG_ENABLE(vc4, ++ AS_HELP_STRING([--disable-vc4], ++ [Enable support for vc4's API (default: auto, enabled on arm)]), ++ [VC4=$enableval], [VC4=auto]) ++ + AC_ARG_ENABLE(install-test-programs, + AS_HELP_STRING([--enable-install-test-programs], + [Install test programs (default: no)]), +@@ -290,6 +295,12 @@ else + *) FREEDRENO=no ;; + esac + fi ++ if test "x$VC4" = xauto; then ++ case $host_cpu in ++ arm*|aarch64) VC4=yes ;; ++ *) VC4=no ;; ++ esac ++ fi + fi + + if test "x$INTEL" != "xno"; then +@@ -396,6 +407,11 @@ if test "x$TEGRA" = xyes; then + AC_DEFINE(HAVE_TEGRA, 1, [Have Tegra support]) + fi + ++AM_CONDITIONAL(HAVE_VC4, [test "x$VC4" = xyes]) ++if test "x$VC4" = xyes; then ++ AC_DEFINE(HAVE_VC4, 1, [Have VC4 support]) ++fi ++ + AM_CONDITIONAL(HAVE_INSTALL_TESTS, [test "x$INSTALL_TESTS" = xyes]) + if test "x$INSTALL_TESTS" = xyes; then + AC_DEFINE(HAVE_INSTALL_TESTS, 1, [Install test programs]) +@@ -505,6 +521,8 @@ AC_CONFIG_FILES([ + freedreno/libdrm_freedreno.pc + tegra/Makefile + tegra/libdrm_tegra.pc ++ vc4/Makefile ++ vc4/libdrm_vc4.pc + tests/Makefile + tests/modeprint/Makefile + tests/modetest/Makefile +@@ -535,4 +553,5 @@ echo " OMAP API $OMAP" + echo " EXYNOS API $EXYNOS" + echo " Freedreno API $FREEDRENO (kgsl: $FREEDRENO_KGSL)" + echo " Tegra API $TEGRA" ++echo " VC4 API $VC4" + echo "" +diff --git a/vc4/Makefile.am b/vc4/Makefile.am +new file mode 100644 +index 0000000..7e486b4 +--- /dev/null ++++ b/vc4/Makefile.am +@@ -0,0 +1,34 @@ ++# Copyright © 2016 Broadcom ++# ++# Permission is hereby granted, free of charge, to any person obtaining a ++# copy of this software and associated documentation files (the "Software"), ++# to deal in the Software without restriction, including without limitation ++# the rights to use, copy, modify, merge, publish, distribute, sublicense, ++# and/or sell copies of the Software, and to permit persons to whom the ++# Software is furnished to do so, subject to the following conditions: ++# ++# The above copyright notice and this permission notice (including the next ++# paragraph) shall be included in all copies or substantial portions of the ++# Software. ++# ++# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS ++# IN THE SOFTWARE. ++ ++include Makefile.sources ++ ++AM_CFLAGS = \ ++ $(WARN_CFLAGS) \ ++ -I$(top_srcdir) \ ++ $(PTHREADSTUBS_CFLAGS) \ ++ $(VALGRIND_CFLAGS) \ ++ -I$(top_srcdir)/include/drm ++ ++libdrm_vc4includedir = ${includedir}/libdrm ++libdrm_vc4include_HEADERS = $(LIBDRM_VC4_H_FILES) ++ ++pkgconfig_DATA = libdrm_vc4.pc +diff --git a/vc4/Makefile.sources b/vc4/Makefile.sources +new file mode 100644 +index 0000000..8bf97ff +--- /dev/null ++++ b/vc4/Makefile.sources +@@ -0,0 +1,3 @@ ++LIBDRM_VC4_H_FILES := \ ++ vc4_packet.h \ ++ vc4_qpu_defines.h +diff --git a/vc4/libdrm_vc4.pc.in b/vc4/libdrm_vc4.pc.in +new file mode 100644 +index 0000000..a92678e +--- /dev/null ++++ b/vc4/libdrm_vc4.pc.in +@@ -0,0 +1,9 @@ ++prefix=@prefix@ ++exec_prefix=@exec_prefix@ ++libdir=@libdir@ ++includedir=@includedir@ ++ ++Name: libdrm_vc4 ++Description: Userspace interface to vc4 kernel DRM services ++Version: @PACKAGE_VERSION@ ++Requires.private: libdrm +diff --git a/vc4/vc4_packet.h b/vc4/vc4_packet.h +new file mode 100644 +index 0000000..e18e0bd +--- /dev/null ++++ b/vc4/vc4_packet.h +@@ -0,0 +1,397 @@ ++/* ++ * Copyright © 2014 Broadcom ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS ++ * IN THE SOFTWARE. ++ */ ++ ++#ifndef VC4_PACKET_H ++#define VC4_PACKET_H ++ ++enum vc4_packet { ++ VC4_PACKET_HALT = 0, ++ VC4_PACKET_NOP = 1, ++ ++ VC4_PACKET_FLUSH = 4, ++ VC4_PACKET_FLUSH_ALL = 5, ++ VC4_PACKET_START_TILE_BINNING = 6, ++ VC4_PACKET_INCREMENT_SEMAPHORE = 7, ++ VC4_PACKET_WAIT_ON_SEMAPHORE = 8, ++ ++ VC4_PACKET_BRANCH = 16, ++ VC4_PACKET_BRANCH_TO_SUB_LIST = 17, ++ VC4_PACKET_RETURN_FROM_SUB_LIST = 18, ++ ++ VC4_PACKET_STORE_MS_TILE_BUFFER = 24, ++ VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF = 25, ++ VC4_PACKET_STORE_FULL_RES_TILE_BUFFER = 26, ++ VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER = 27, ++ VC4_PACKET_STORE_TILE_BUFFER_GENERAL = 28, ++ VC4_PACKET_LOAD_TILE_BUFFER_GENERAL = 29, ++ ++ VC4_PACKET_GL_INDEXED_PRIMITIVE = 32, ++ VC4_PACKET_GL_ARRAY_PRIMITIVE = 33, ++ ++ VC4_PACKET_COMPRESSED_PRIMITIVE = 48, ++ VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE = 49, ++ ++ VC4_PACKET_PRIMITIVE_LIST_FORMAT = 56, ++ ++ VC4_PACKET_GL_SHADER_STATE = 64, ++ VC4_PACKET_NV_SHADER_STATE = 65, ++ VC4_PACKET_VG_SHADER_STATE = 66, ++ ++ VC4_PACKET_CONFIGURATION_BITS = 96, ++ VC4_PACKET_FLAT_SHADE_FLAGS = 97, ++ VC4_PACKET_POINT_SIZE = 98, ++ VC4_PACKET_LINE_WIDTH = 99, ++ VC4_PACKET_RHT_X_BOUNDARY = 100, ++ VC4_PACKET_DEPTH_OFFSET = 101, ++ VC4_PACKET_CLIP_WINDOW = 102, ++ VC4_PACKET_VIEWPORT_OFFSET = 103, ++ VC4_PACKET_Z_CLIPPING = 104, ++ VC4_PACKET_CLIPPER_XY_SCALING = 105, ++ VC4_PACKET_CLIPPER_Z_SCALING = 106, ++ ++ VC4_PACKET_TILE_BINNING_MODE_CONFIG = 112, ++ VC4_PACKET_TILE_RENDERING_MODE_CONFIG = 113, ++ VC4_PACKET_CLEAR_COLORS = 114, ++ VC4_PACKET_TILE_COORDINATES = 115, ++ ++ /* Not an actual hardware packet -- this is what we use to put ++ * references to GEM bos in the command stream, since we need the u32 ++ * int the actual address packet in order to store the offset from the ++ * start of the BO. ++ */ ++ VC4_PACKET_GEM_HANDLES = 254, ++} __attribute__ ((__packed__)); ++ ++#define VC4_PACKET_HALT_SIZE 1 ++#define VC4_PACKET_NOP_SIZE 1 ++#define VC4_PACKET_FLUSH_SIZE 1 ++#define VC4_PACKET_FLUSH_ALL_SIZE 1 ++#define VC4_PACKET_START_TILE_BINNING_SIZE 1 ++#define VC4_PACKET_INCREMENT_SEMAPHORE_SIZE 1 ++#define VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE 1 ++#define VC4_PACKET_BRANCH_SIZE 5 ++#define VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE 5 ++#define VC4_PACKET_RETURN_FROM_SUB_LIST_SIZE 1 ++#define VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE 1 ++#define VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF_SIZE 1 ++#define VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE 5 ++#define VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE 5 ++#define VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE 7 ++#define VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE 7 ++#define VC4_PACKET_GL_INDEXED_PRIMITIVE_SIZE 14 ++#define VC4_PACKET_GL_ARRAY_PRIMITIVE_SIZE 10 ++#define VC4_PACKET_COMPRESSED_PRIMITIVE_SIZE 1 ++#define VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE_SIZE 1 ++#define VC4_PACKET_PRIMITIVE_LIST_FORMAT_SIZE 2 ++#define VC4_PACKET_GL_SHADER_STATE_SIZE 5 ++#define VC4_PACKET_NV_SHADER_STATE_SIZE 5 ++#define VC4_PACKET_VG_SHADER_STATE_SIZE 5 ++#define VC4_PACKET_CONFIGURATION_BITS_SIZE 4 ++#define VC4_PACKET_FLAT_SHADE_FLAGS_SIZE 5 ++#define VC4_PACKET_POINT_SIZE_SIZE 5 ++#define VC4_PACKET_LINE_WIDTH_SIZE 5 ++#define VC4_PACKET_RHT_X_BOUNDARY_SIZE 3 ++#define VC4_PACKET_DEPTH_OFFSET_SIZE 5 ++#define VC4_PACKET_CLIP_WINDOW_SIZE 9 ++#define VC4_PACKET_VIEWPORT_OFFSET_SIZE 5 ++#define VC4_PACKET_Z_CLIPPING_SIZE 9 ++#define VC4_PACKET_CLIPPER_XY_SCALING_SIZE 9 ++#define VC4_PACKET_CLIPPER_Z_SCALING_SIZE 9 ++#define VC4_PACKET_TILE_BINNING_MODE_CONFIG_SIZE 16 ++#define VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE 11 ++#define VC4_PACKET_CLEAR_COLORS_SIZE 14 ++#define VC4_PACKET_TILE_COORDINATES_SIZE 3 ++#define VC4_PACKET_GEM_HANDLES_SIZE 9 ++ ++#define VC4_MASK(high, low) (((1 << ((high) - (low) + 1)) - 1) << (low)) ++/* Using the GNU statement expression extension */ ++#define VC4_SET_FIELD(value, field) \ ++ ({ \ ++ uint32_t fieldval = (value) << field ## _SHIFT; \ ++ assert((fieldval & ~ field ## _MASK) == 0); \ ++ fieldval & field ## _MASK; \ ++ }) ++ ++#define VC4_GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) ++ ++/** @{ ++ * Bits used by packets like VC4_PACKET_STORE_TILE_BUFFER_GENERAL and ++ * VC4_PACKET_TILE_RENDERING_MODE_CONFIG. ++*/ ++#define VC4_TILING_FORMAT_LINEAR 0 ++#define VC4_TILING_FORMAT_T 1 ++#define VC4_TILING_FORMAT_LT 2 ++/** @} */ ++ ++/** @{ ++ * ++ * low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and ++ * VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER. ++ */ ++#define VC4_LOADSTORE_FULL_RES_EOF (1 << 3) ++#define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL (1 << 2) ++#define VC4_LOADSTORE_FULL_RES_DISABLE_ZS (1 << 1) ++#define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR (1 << 0) ++ ++/** @{ ++ * ++ * byte 2 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and ++ * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL (low bits of the address) ++ */ ++ ++#define VC4_LOADSTORE_TILE_BUFFER_EOF (1 << 3) ++#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK (1 << 2) ++#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS (1 << 1) ++#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR (1 << 0) ++ ++/** @} */ ++ ++/** @{ ++ * ++ * byte 0-1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and ++ * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL ++ */ ++#define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR (1 << 15) ++#define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR (1 << 14) ++#define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR (1 << 13) ++#define VC4_STORE_TILE_BUFFER_DISABLE_SWAP (1 << 12) ++ ++#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK VC4_MASK(9, 8) ++#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT 8 ++#define VC4_LOADSTORE_TILE_BUFFER_RGBA8888 0 ++#define VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER 1 ++#define VC4_LOADSTORE_TILE_BUFFER_BGR565 2 ++/** @} */ ++ ++/** @{ ++ * ++ * byte 0 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and ++ * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL ++ */ ++#define VC4_STORE_TILE_BUFFER_MODE_MASK VC4_MASK(7, 6) ++#define VC4_STORE_TILE_BUFFER_MODE_SHIFT 6 ++#define VC4_STORE_TILE_BUFFER_MODE_SAMPLE0 (0 << 6) ++#define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X4 (1 << 6) ++#define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X16 (2 << 6) ++ ++/** The values of the field are VC4_TILING_FORMAT_* */ ++#define VC4_LOADSTORE_TILE_BUFFER_TILING_MASK VC4_MASK(5, 4) ++#define VC4_LOADSTORE_TILE_BUFFER_TILING_SHIFT 4 ++ ++#define VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK VC4_MASK(2, 0) ++#define VC4_LOADSTORE_TILE_BUFFER_BUFFER_SHIFT 0 ++#define VC4_LOADSTORE_TILE_BUFFER_NONE 0 ++#define VC4_LOADSTORE_TILE_BUFFER_COLOR 1 ++#define VC4_LOADSTORE_TILE_BUFFER_ZS 2 ++#define VC4_LOADSTORE_TILE_BUFFER_Z 3 ++#define VC4_LOADSTORE_TILE_BUFFER_VG_MASK 4 ++#define VC4_LOADSTORE_TILE_BUFFER_FULL 5 ++/** @} */ ++ ++#define VC4_INDEX_BUFFER_U8 (0 << 4) ++#define VC4_INDEX_BUFFER_U16 (1 << 4) ++ ++/* This flag is only present in NV shader state. */ ++#define VC4_SHADER_FLAG_SHADED_CLIP_COORDS (1 << 3) ++#define VC4_SHADER_FLAG_ENABLE_CLIPPING (1 << 2) ++#define VC4_SHADER_FLAG_VS_POINT_SIZE (1 << 1) ++#define VC4_SHADER_FLAG_FS_SINGLE_THREAD (1 << 0) ++ ++/** @{ byte 2 of config bits. */ ++#define VC4_CONFIG_BITS_EARLY_Z_UPDATE (1 << 1) ++#define VC4_CONFIG_BITS_EARLY_Z (1 << 0) ++/** @} */ ++ ++/** @{ byte 1 of config bits. */ ++#define VC4_CONFIG_BITS_Z_UPDATE (1 << 7) ++/** same values in this 3-bit field as PIPE_FUNC_* */ ++#define VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT 4 ++#define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE (1 << 3) ++ ++#define VC4_CONFIG_BITS_COVERAGE_UPDATE_NONZERO (0 << 1) ++#define VC4_CONFIG_BITS_COVERAGE_UPDATE_ODD (1 << 1) ++#define VC4_CONFIG_BITS_COVERAGE_UPDATE_OR (2 << 1) ++#define VC4_CONFIG_BITS_COVERAGE_UPDATE_ZERO (3 << 1) ++ ++#define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT (1 << 0) ++/** @} */ ++ ++/** @{ byte 0 of config bits. */ ++#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_NONE (0 << 6) ++#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X (1 << 6) ++#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_16X (2 << 6) ++#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_MASK (3 << 6) ++ ++#define VC4_CONFIG_BITS_AA_POINTS_AND_LINES (1 << 4) ++#define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET (1 << 3) ++#define VC4_CONFIG_BITS_CW_PRIMITIVES (1 << 2) ++#define VC4_CONFIG_BITS_ENABLE_PRIM_BACK (1 << 1) ++#define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT (1 << 0) ++/** @} */ ++ ++/** @{ bits in the last u8 of VC4_PACKET_TILE_BINNING_MODE_CONFIG */ ++#define VC4_BIN_CONFIG_DB_NON_MS (1 << 7) ++ ++#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK VC4_MASK(6, 5) ++#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_SHIFT 5 ++#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32 0 ++#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_64 1 ++#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128 2 ++#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_256 3 ++ ++#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_MASK VC4_MASK(4, 3) ++#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_SHIFT 3 ++#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32 0 ++#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_64 1 ++#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_128 2 ++#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_256 3 ++ ++#define VC4_BIN_CONFIG_AUTO_INIT_TSDA (1 << 2) ++#define VC4_BIN_CONFIG_TILE_BUFFER_64BIT (1 << 1) ++#define VC4_BIN_CONFIG_MS_MODE_4X (1 << 0) ++/** @} */ ++ ++/** @{ bits in the last u16 of VC4_PACKET_TILE_RENDERING_MODE_CONFIG */ ++#define VC4_RENDER_CONFIG_DB_NON_MS (1 << 12) ++#define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE (1 << 11) ++#define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G (1 << 10) ++#define VC4_RENDER_CONFIG_COVERAGE_MODE (1 << 9) ++#define VC4_RENDER_CONFIG_ENABLE_VG_MASK (1 << 8) ++ ++/** The values of the field are VC4_TILING_FORMAT_* */ ++#define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK VC4_MASK(7, 6) ++#define VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT 6 ++ ++#define VC4_RENDER_CONFIG_DECIMATE_MODE_1X (0 << 4) ++#define VC4_RENDER_CONFIG_DECIMATE_MODE_4X (1 << 4) ++#define VC4_RENDER_CONFIG_DECIMATE_MODE_16X (2 << 4) ++#define VC4_RENDER_CONFIG_DECIMATE_MODE_MASK (3 << 4) ++ ++#define VC4_RENDER_CONFIG_FORMAT_MASK VC4_MASK(3, 2) ++#define VC4_RENDER_CONFIG_FORMAT_SHIFT 2 ++#define VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED 0 ++#define VC4_RENDER_CONFIG_FORMAT_RGBA8888 1 ++#define VC4_RENDER_CONFIG_FORMAT_BGR565 2 ++ ++#define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT (1 << 1) ++#define VC4_RENDER_CONFIG_MS_MODE_4X (1 << 0) ++ ++#define VC4_PRIMITIVE_LIST_FORMAT_16_INDEX (1 << 4) ++#define VC4_PRIMITIVE_LIST_FORMAT_32_XY (3 << 4) ++#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_POINTS (0 << 0) ++#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_LINES (1 << 0) ++#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES (2 << 0) ++#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_RHT (3 << 0) ++ ++enum vc4_texture_data_type { ++ VC4_TEXTURE_TYPE_RGBA8888 = 0, ++ VC4_TEXTURE_TYPE_RGBX8888 = 1, ++ VC4_TEXTURE_TYPE_RGBA4444 = 2, ++ VC4_TEXTURE_TYPE_RGBA5551 = 3, ++ VC4_TEXTURE_TYPE_RGB565 = 4, ++ VC4_TEXTURE_TYPE_LUMINANCE = 5, ++ VC4_TEXTURE_TYPE_ALPHA = 6, ++ VC4_TEXTURE_TYPE_LUMALPHA = 7, ++ VC4_TEXTURE_TYPE_ETC1 = 8, ++ VC4_TEXTURE_TYPE_S16F = 9, ++ VC4_TEXTURE_TYPE_S8 = 10, ++ VC4_TEXTURE_TYPE_S16 = 11, ++ VC4_TEXTURE_TYPE_BW1 = 12, ++ VC4_TEXTURE_TYPE_A4 = 13, ++ VC4_TEXTURE_TYPE_A1 = 14, ++ VC4_TEXTURE_TYPE_RGBA64 = 15, ++ VC4_TEXTURE_TYPE_RGBA32R = 16, ++ VC4_TEXTURE_TYPE_YUV422R = 17, ++}; ++ ++#define VC4_TEX_P0_OFFSET_MASK VC4_MASK(31, 12) ++#define VC4_TEX_P0_OFFSET_SHIFT 12 ++#define VC4_TEX_P0_CSWIZ_MASK VC4_MASK(11, 10) ++#define VC4_TEX_P0_CSWIZ_SHIFT 10 ++#define VC4_TEX_P0_CMMODE_MASK VC4_MASK(9, 9) ++#define VC4_TEX_P0_CMMODE_SHIFT 9 ++#define VC4_TEX_P0_FLIPY_MASK VC4_MASK(8, 8) ++#define VC4_TEX_P0_FLIPY_SHIFT 8 ++#define VC4_TEX_P0_TYPE_MASK VC4_MASK(7, 4) ++#define VC4_TEX_P0_TYPE_SHIFT 4 ++#define VC4_TEX_P0_MIPLVLS_MASK VC4_MASK(3, 0) ++#define VC4_TEX_P0_MIPLVLS_SHIFT 0 ++ ++#define VC4_TEX_P1_TYPE4_MASK VC4_MASK(31, 31) ++#define VC4_TEX_P1_TYPE4_SHIFT 31 ++#define VC4_TEX_P1_HEIGHT_MASK VC4_MASK(30, 20) ++#define VC4_TEX_P1_HEIGHT_SHIFT 20 ++#define VC4_TEX_P1_ETCFLIP_MASK VC4_MASK(19, 19) ++#define VC4_TEX_P1_ETCFLIP_SHIFT 19 ++#define VC4_TEX_P1_WIDTH_MASK VC4_MASK(18, 8) ++#define VC4_TEX_P1_WIDTH_SHIFT 8 ++ ++#define VC4_TEX_P1_MAGFILT_MASK VC4_MASK(7, 7) ++#define VC4_TEX_P1_MAGFILT_SHIFT 7 ++# define VC4_TEX_P1_MAGFILT_LINEAR 0 ++# define VC4_TEX_P1_MAGFILT_NEAREST 1 ++ ++#define VC4_TEX_P1_MINFILT_MASK VC4_MASK(6, 4) ++#define VC4_TEX_P1_MINFILT_SHIFT 4 ++# define VC4_TEX_P1_MINFILT_LINEAR 0 ++# define VC4_TEX_P1_MINFILT_NEAREST 1 ++# define VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR 2 ++# define VC4_TEX_P1_MINFILT_NEAR_MIP_LIN 3 ++# define VC4_TEX_P1_MINFILT_LIN_MIP_NEAR 4 ++# define VC4_TEX_P1_MINFILT_LIN_MIP_LIN 5 ++ ++#define VC4_TEX_P1_WRAP_T_MASK VC4_MASK(3, 2) ++#define VC4_TEX_P1_WRAP_T_SHIFT 2 ++#define VC4_TEX_P1_WRAP_S_MASK VC4_MASK(1, 0) ++#define VC4_TEX_P1_WRAP_S_SHIFT 0 ++# define VC4_TEX_P1_WRAP_REPEAT 0 ++# define VC4_TEX_P1_WRAP_CLAMP 1 ++# define VC4_TEX_P1_WRAP_MIRROR 2 ++# define VC4_TEX_P1_WRAP_BORDER 3 ++ ++#define VC4_TEX_P2_PTYPE_MASK VC4_MASK(31, 30) ++#define VC4_TEX_P2_PTYPE_SHIFT 30 ++# define VC4_TEX_P2_PTYPE_IGNORED 0 ++# define VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE 1 ++# define VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS 2 ++# define VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS 3 ++ ++/* VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE bits */ ++#define VC4_TEX_P2_CMST_MASK VC4_MASK(29, 12) ++#define VC4_TEX_P2_CMST_SHIFT 12 ++#define VC4_TEX_P2_BSLOD_MASK VC4_MASK(0, 0) ++#define VC4_TEX_P2_BSLOD_SHIFT 0 ++ ++/* VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS */ ++#define VC4_TEX_P2_CHEIGHT_MASK VC4_MASK(22, 12) ++#define VC4_TEX_P2_CHEIGHT_SHIFT 12 ++#define VC4_TEX_P2_CWIDTH_MASK VC4_MASK(10, 0) ++#define VC4_TEX_P2_CWIDTH_SHIFT 0 ++ ++/* VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS */ ++#define VC4_TEX_P2_CYOFF_MASK VC4_MASK(22, 12) ++#define VC4_TEX_P2_CYOFF_SHIFT 12 ++#define VC4_TEX_P2_CXOFF_MASK VC4_MASK(10, 0) ++#define VC4_TEX_P2_CXOFF_SHIFT 0 ++ ++#endif /* VC4_PACKET_H */ +diff --git a/vc4/vc4_qpu_defines.h b/vc4/vc4_qpu_defines.h +new file mode 100644 +index 0000000..26fcf50 +--- /dev/null ++++ b/vc4/vc4_qpu_defines.h +@@ -0,0 +1,274 @@ ++/* ++ * Copyright © 2014 Broadcom ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS ++ * IN THE SOFTWARE. ++ */ ++ ++#ifndef VC4_QPU_DEFINES_H ++#define VC4_QPU_DEFINES_H ++ ++enum qpu_op_add { ++ QPU_A_NOP, ++ QPU_A_FADD, ++ QPU_A_FSUB, ++ QPU_A_FMIN, ++ QPU_A_FMAX, ++ QPU_A_FMINABS, ++ QPU_A_FMAXABS, ++ QPU_A_FTOI, ++ QPU_A_ITOF, ++ QPU_A_ADD = 12, ++ QPU_A_SUB, ++ QPU_A_SHR, ++ QPU_A_ASR, ++ QPU_A_ROR, ++ QPU_A_SHL, ++ QPU_A_MIN, ++ QPU_A_MAX, ++ QPU_A_AND, ++ QPU_A_OR, ++ QPU_A_XOR, ++ QPU_A_NOT, ++ QPU_A_CLZ, ++ QPU_A_V8ADDS = 30, ++ QPU_A_V8SUBS = 31, ++}; ++ ++enum qpu_op_mul { ++ QPU_M_NOP, ++ QPU_M_FMUL, ++ QPU_M_MUL24, ++ QPU_M_V8MULD, ++ QPU_M_V8MIN, ++ QPU_M_V8MAX, ++ QPU_M_V8ADDS, ++ QPU_M_V8SUBS, ++}; ++ ++enum qpu_raddr { ++ QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */ ++ /* 0-31 are the plain regfile a or b fields */ ++ QPU_R_UNIF = 32, ++ QPU_R_VARY = 35, ++ QPU_R_ELEM_QPU = 38, ++ QPU_R_NOP, ++ QPU_R_XY_PIXEL_COORD = 41, ++ QPU_R_MS_REV_FLAGS = 42, ++ QPU_R_VPM = 48, ++ QPU_R_VPM_LD_BUSY, ++ QPU_R_VPM_LD_WAIT, ++ QPU_R_MUTEX_ACQUIRE, ++}; ++ ++enum qpu_waddr { ++ /* 0-31 are the plain regfile a or b fields */ ++ QPU_W_ACC0 = 32, /* aka r0 */ ++ QPU_W_ACC1, ++ QPU_W_ACC2, ++ QPU_W_ACC3, ++ QPU_W_TMU_NOSWAP, ++ QPU_W_ACC5, ++ QPU_W_HOST_INT, ++ QPU_W_NOP, ++ QPU_W_UNIFORMS_ADDRESS, ++ QPU_W_QUAD_XY, /* X for regfile a, Y for regfile b */ ++ QPU_W_MS_FLAGS = 42, ++ QPU_W_REV_FLAG = 42, ++ QPU_W_TLB_STENCIL_SETUP = 43, ++ QPU_W_TLB_Z, ++ QPU_W_TLB_COLOR_MS, ++ QPU_W_TLB_COLOR_ALL, ++ QPU_W_TLB_ALPHA_MASK, ++ QPU_W_VPM, ++ QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */ ++ QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */ ++ QPU_W_MUTEX_RELEASE, ++ QPU_W_SFU_RECIP, ++ QPU_W_SFU_RECIPSQRT, ++ QPU_W_SFU_EXP, ++ QPU_W_SFU_LOG, ++ QPU_W_TMU0_S, ++ QPU_W_TMU0_T, ++ QPU_W_TMU0_R, ++ QPU_W_TMU0_B, ++ QPU_W_TMU1_S, ++ QPU_W_TMU1_T, ++ QPU_W_TMU1_R, ++ QPU_W_TMU1_B, ++}; ++ ++enum qpu_sig_bits { ++ QPU_SIG_SW_BREAKPOINT, ++ QPU_SIG_NONE, ++ QPU_SIG_THREAD_SWITCH, ++ QPU_SIG_PROG_END, ++ QPU_SIG_WAIT_FOR_SCOREBOARD, ++ QPU_SIG_SCOREBOARD_UNLOCK, ++ QPU_SIG_LAST_THREAD_SWITCH, ++ QPU_SIG_COVERAGE_LOAD, ++ QPU_SIG_COLOR_LOAD, ++ QPU_SIG_COLOR_LOAD_END, ++ QPU_SIG_LOAD_TMU0, ++ QPU_SIG_LOAD_TMU1, ++ QPU_SIG_ALPHA_MASK_LOAD, ++ QPU_SIG_SMALL_IMM, ++ QPU_SIG_LOAD_IMM, ++ QPU_SIG_BRANCH ++}; ++ ++enum qpu_mux { ++ /* hardware mux values */ ++ QPU_MUX_R0, ++ QPU_MUX_R1, ++ QPU_MUX_R2, ++ QPU_MUX_R3, ++ QPU_MUX_R4, ++ QPU_MUX_R5, ++ QPU_MUX_A, ++ QPU_MUX_B, ++ ++ /** ++ * Non-hardware mux value, stores a small immediate field to be ++ * programmed into raddr_b in the qpu_reg.index. ++ */ ++ QPU_MUX_SMALL_IMM, ++}; ++ ++enum qpu_cond { ++ QPU_COND_NEVER, ++ QPU_COND_ALWAYS, ++ QPU_COND_ZS, ++ QPU_COND_ZC, ++ QPU_COND_NS, ++ QPU_COND_NC, ++ QPU_COND_CS, ++ QPU_COND_CC, ++}; ++ ++enum qpu_pack_mul { ++ QPU_PACK_MUL_NOP, ++ QPU_PACK_MUL_8888 = 3, /* replicated to each 8 bits of the 32-bit dst. */ ++ QPU_PACK_MUL_8A, ++ QPU_PACK_MUL_8B, ++ QPU_PACK_MUL_8C, ++ QPU_PACK_MUL_8D, ++}; ++ ++enum qpu_pack_a { ++ QPU_PACK_A_NOP, ++ /* convert to 16 bit float if float input, or to int16. */ ++ QPU_PACK_A_16A, ++ QPU_PACK_A_16B, ++ /* replicated to each 8 bits of the 32-bit dst. */ ++ QPU_PACK_A_8888, ++ /* Convert to 8-bit unsigned int. */ ++ QPU_PACK_A_8A, ++ QPU_PACK_A_8B, ++ QPU_PACK_A_8C, ++ QPU_PACK_A_8D, ++ ++ /* Saturating variants of the previous instructions. */ ++ QPU_PACK_A_32_SAT, /* int-only */ ++ QPU_PACK_A_16A_SAT, /* int or float */ ++ QPU_PACK_A_16B_SAT, ++ QPU_PACK_A_8888_SAT, ++ QPU_PACK_A_8A_SAT, ++ QPU_PACK_A_8B_SAT, ++ QPU_PACK_A_8C_SAT, ++ QPU_PACK_A_8D_SAT, ++}; ++ ++enum qpu_unpack { ++ QPU_UNPACK_NOP, ++ QPU_UNPACK_16A, ++ QPU_UNPACK_16B, ++ QPU_UNPACK_8D_REP, ++ QPU_UNPACK_8A, ++ QPU_UNPACK_8B, ++ QPU_UNPACK_8C, ++ QPU_UNPACK_8D, ++}; ++ ++#define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low)) ++/* Using the GNU statement expression extension */ ++#define QPU_SET_FIELD(value, field) \ ++ ({ \ ++ uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \ ++ assert((fieldval & ~ field ## _MASK) == 0); \ ++ fieldval & field ## _MASK; \ ++ }) ++ ++#define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) ++ ++#define QPU_UPDATE_FIELD(inst, value, field) \ ++ (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field)) ++ ++#define QPU_SIG_SHIFT 60 ++#define QPU_SIG_MASK QPU_MASK(63, 60) ++ ++#define QPU_UNPACK_SHIFT 57 ++#define QPU_UNPACK_MASK QPU_MASK(59, 57) ++ ++/** ++ * If set, the pack field means PACK_MUL or R4 packing, instead of normal ++ * regfile a packing. ++ */ ++#define QPU_PM ((uint64_t)1 << 56) ++ ++#define QPU_PACK_SHIFT 52 ++#define QPU_PACK_MASK QPU_MASK(55, 52) ++ ++#define QPU_COND_ADD_SHIFT 49 ++#define QPU_COND_ADD_MASK QPU_MASK(51, 49) ++#define QPU_COND_MUL_SHIFT 46 ++#define QPU_COND_MUL_MASK QPU_MASK(48, 46) ++ ++#define QPU_SF ((uint64_t)1 << 45) ++ ++#define QPU_WADDR_ADD_SHIFT 38 ++#define QPU_WADDR_ADD_MASK QPU_MASK(43, 38) ++#define QPU_WADDR_MUL_SHIFT 32 ++#define QPU_WADDR_MUL_MASK QPU_MASK(37, 32) ++ ++#define QPU_OP_MUL_SHIFT 29 ++#define QPU_OP_MUL_MASK QPU_MASK(31, 29) ++ ++#define QPU_RADDR_A_SHIFT 18 ++#define QPU_RADDR_A_MASK QPU_MASK(23, 18) ++#define QPU_RADDR_B_SHIFT 12 ++#define QPU_RADDR_B_MASK QPU_MASK(17, 12) ++#define QPU_SMALL_IMM_SHIFT 12 ++#define QPU_SMALL_IMM_MASK QPU_MASK(17, 12) ++ ++#define QPU_ADD_A_SHIFT 9 ++#define QPU_ADD_A_MASK QPU_MASK(11, 9) ++#define QPU_ADD_B_SHIFT 6 ++#define QPU_ADD_B_MASK QPU_MASK(8, 6) ++#define QPU_MUL_A_SHIFT 3 ++#define QPU_MUL_A_MASK QPU_MASK(5, 3) ++#define QPU_MUL_B_SHIFT 0 ++#define QPU_MUL_B_MASK QPU_MASK(2, 0) ++ ++#define QPU_WS ((uint64_t)1 << 44) ++ ++#define QPU_OP_ADD_SHIFT 24 ++#define QPU_OP_ADD_MASK QPU_MASK(28, 24) ++ ++#endif /* VC4_QPU_DEFINES_H */ +-- +2.7.4 + |